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ds1mx7 ds1 mapper 7-channel microprocessor interface test access port interface for line transceiver serial interface (x 7) system clocks boundary scan ds1 dual rail / nrz data & clocks (x 7) telecom bus interface (x 1) txc-04201b line side system side +5v line transceiver common control interface auxiliary port ring port add bus drop bus 18 13 6 3 4 4 2 3510 the ds1mx7 is a seven-channel byte-synchronous and asynchronous ds1 mapper. both sonet and sdh map- pings are provided per bellcore gr-253-core (vt1.5) and itu-t g.707 3-96 (tu-11). a single add/drop tele- com bus is provided that can operate at either 6.48 or 19.44 mhz, which is compatible with other transwitch devices. vt1.5/tu-11 pointer tracking and overhead extraction/processing with full error and alarm control is provided. vt1.5/tu-11 pointer calculation and overhead assembly is also provided. alarm and error mappings from drop to add and sonet/sdh to/from ds1 are pro- vided. jitter performance is achieved with a fully digital threshold modulator and dpll that meets gr-253-core mtie requirements without external de-jitter buffers. for the ds1 line, ami, b8zs and nrz line codes are sup- ported with full alarm detection and generation per ansi t1.231-1997 draft. each channel is independently pro- grammable for mixed service applications. access to sta- tus and control bits is provided via an intel/motorola- compatible microprocessor interface. diagnostic, test, and maintenance functions are provided, including boundary scan, prbs generator/analyzer and loopbacks. ? seven independent 1.544 mbit/s ds1 mappers single byte-parallel telecom bus @ 6.48 mhz (28 slots) or 19.44 mhz (84 slots) floating vt1.5 byte-synchronous mapping with signaling only for use with or without a slip buffer asynchronous mapping for ds1 sonet mapping (vt1.5) or sdh mapping (tu-11 in au-3 or tu-11 in tug-3) ami, b8zs or nrz codec for ds1s serial i/o for control of ds1 line interface transceivers or framers telecom bus and ds1 loopbacks with integral prbs generator and analyzer vt1.5/tu-11 pointer tracking and generation vt1.5/tu-11 overhead processing and insertion one-second latched performance registers and counters ds1 alarm detection and generation auxiliary port for j2, v5, z6/n2, z7/k4 and o-bit access ring port for ushr/p support gapped clock option for internet applications without need for a framer intel / motorola-compatible microprocessor interface 3-bit rdi support boundary scan capability (ieee 1149.1) single +5 v, 5 % power supply 208-pin plastic quad flat package sonet/sdh terminal or add/drop multiplexers sup- porting both asynchronous and byte-synchronous modes unidirectional or bidirectional ring applications sonet remote digital terminal equipment sonet cpe equipment requiring access to ds0s sonet/sdh test equipment internet access equipment ds1mx7 device ds1 mapper 7-channel txc-04201b document number: txc-04201b-mb ed. 4, september 2001 u.s. patents no. 4,967,405; 5,033,064; 5,040,170; 5,265,096; 5,289,507; 5,297,180; 5,528,598; 5,535,218 u.s. and/or foreign patents issued or pending copyright ? 2001 transwitch corporation transwitch and txc are registered trademarks of transwitch corporation data sheet proprietary transwitch corporation information for use solely by its customers applications description features transwitch corporation ? 3 enterprise drive shelton, connecticut 06484 usa tel: 203-929-8810 fax: 203-926-9453 www.transwitch.com
- 2 of 154 - txc-04201b-mb ed. 4, september 2001 proprietary transwitch corporation information for use solely by its customers ds1mx7 txc-04201b data sheet table of contents section page list of figures ............................................................................................................... .....................3 feature list................................................................................................................... ..................... 4 features that are independently selectable for each of the mappers........................................ 4 features that are only selectable for the seven mappers as a group....................................... 7 block diagram .................................................................................................................. ................. 9 block diagram description ...................................................................................................... ........ 10 pin diagram .................................................................................................................... ................. 15 pin descriptions............................................................................................................... ................ 16 absolute maximum ratings and environmental limitations............................................................ 25 thermal characteristics........................................................................................................ ........... 25 power requirements ............................................................................................................. .......... 25 input, output and input/output parameters..................................................................................... 26 timing characteristics ......................................................................................................... ............ 29 operation ...................................................................................................................... ................... 46 general mapper application overview ..................................................................................... 46 line interface selection ....................................................................................................... ..... 46 asynchronous operation with the line interface............................................................... 47 byte-synchronous operation with the line interface......................................................... 49 receive data and signaling highway operation .............................................................. 49 transmit data and signaling highway operation ............................................................. 52 the synchronizer, mapper and overhead generator ....................................................... 54 pointer generation and telecom bus slot selection ........................................................ 57 vt/tu pointer tracking and telecom bus slot selection................................................. 60 the demapper .................................................................................................................. 63 desynchronization and pointer leak rate calculations ................................................... 65 jitter measurements ............................................................................................................ ..... 68 microprocessor interface and common control/status i/o...................................................... 74 serial port control interface .................................................................................................. ... 77 ds1mx7 channel testing using the prbs generator and analyzer ............................... 78 telecom bus interface.......................................................................................................... .... 79 multiplex format and mapping information .............................................................................. 83 auxiliary port ................................................................................................................. ........... 89 ring port...................................................................................................................... ............. 91 test access port ............................................................................................................... ....... 91 boundary scan support .................................................................................................... 92 device reset procedure......................................................................................................... .. 99 memory map..................................................................................................................... ............. 100 memory map descriptions ........................................................................................................ ..... 104 common memory map ........................................................................................................... 10 4 per channel control registers............................................................................................... 12 0 per channel status registers ................................................................................................ 13 1 application diagrams........................................................................................................... .......... 144 package information............................................................................................................ .......... 146 ordering information........................................................................................................... ........... 147 related products ............................................................................................................... ............ 147 standards documentation sources ............................................................................................... 148 list of data sheet changes..................................................................................................... ...... 150 documentation update registration form* .............................................................................. 153 * please note that transwitch provides documentation for all of its products. current editions of many documents are available from the products page of the transwitch web site at www.transwitch.com. customers who are using a transwitch product, or planning to do so, should register with the transwitch marketing department to receive relevant updated and supplemental documentation as it is issued. they should also contact the applications engineering department to ensure that they are provided with the latest available information about the product, especially before undertaking development of new designs incorporating the product.
- 3 of 154 - txc-04201b-mb ed. 4, september 2001 ds1mx7 txc-04201b data sheet proprietary transwitch corporation information for use solely by its customers list of figures figure page 1 ds1mx7 txc-04201b block diagram................................................................................ 9 2 vt1.5/ tu-11 asynchronous and byte-synchronous mappings........................................ 12 3 ds1mx7 txc-04201b pin diagram ................................................................................. 15 4 tributary input timing ....................................................................................................... 29 5 tributary output timing..................................................................................................... 3 0 6 signaling highway structure ............................................................................................ 31 7 serial control port structure and timing .......................................................................... 32 8 telecom bus input timing - 6.48 mhz operation ............................................................. 33 9 telecom bus input timing - 19.44 mhz operation ........................................................... 34 10 telecom bus output timing - 6.48 mhz operation .......................................................... 35 11 telecom bus output timing - 19.44 mhz operation ........................................................ 36 12 auxiliary port timing ........................................................................................................ . 37 13 ring port timing............................................................................................................. ... 38 14 datacom mode output timing .......................................................................................... 39 15 datacom mode input timing ............................................................................................. 40 16 intel microprocessor read cycle timing........................................................................... 41 17 motorola microprocessor read cycle timing ................................................................... 42 18 intel microprocessor write cycle timing .......................................................................... 43 19 motorola microprocessor write cycle timing.................................................................... 44 20 boundary scan timing ...................................................................................................... 45 21 line interface for dual unipolar mode............................................................................... 48 22 line interface for nrz mode ............................................................................................. 48 23 byte-synchronous interface to a ds1 framer ................................................................... 49 24 system interface receive framing format....................................................................... 51 25 system interface receive signaling format ..................................................................... 51 26 system interface transmit framing format...................................................................... 53 27 system interface transmit signaling format .................................................................... 53 28 vt/tu pointer tracking state machine............................................................................. 62 29 pointer leak rate algorithm ............................................................................................. 67 30 jitter tolerance test setup ............................................................................................... 68 31 jitter tolerance measurements......................................................................................... 69 32 jitter transfer test setup.................................................................................................. 70 33 jitter transfer measurements ........................................................................................... 70 34 jitter generation test setup ............................................................................................. 71 35 standard pointer test sequences .................................................................................... 73 36 shadow register operation .............................................................................................. 77 37 serial interface operation ................................................................................................. 7 8 38 loopbacks and built-in prbs testing of the ds1mx7 ..................................................... 79 39 telecom bus structure; sonet or vc-3 sdh; telecom bus @ 6.48 mhz ..................... 81 40 telecom bus structure; tug-3 sdh; telecom bus @ 19.44 mhz .................................. 82 41 sts-1 spe mapping ......................................................................................................... 83 42 sts-3/au-3 mapping ........................................................................................................ 85 43 stm-1/vc-4 mapping........................................................................................................ 87 44 auxiliary port operation .................................................................................................... 89 45 auxiliary port address designation ................................................................................... 90 46 ring port operation.......................................................................................................... . 91 47 boundary scan schematic ................................................................................................ 93 48 ds1mx7 txc-04201b applications................................................................................ 144 49 some ds1mx7 txc-04201b byte-synchronous applications........................................ 145 50 ds1mx7 txc-04201b 208-pin plastic quad flat package ........................................... 146
- 4 of 154 - txc-04201b-mb ed. 4, september 2001 proprietary transwitch corporation information for use solely by its customers ds1mx7 txc-04201b data sheet feature list the ds1mx7 device is a highly-featured seven-channel ds1 (t1) mapper for use in a wide variety of interface, transmission and switching applications. seven independent ds1 asynchronous / byte-synchronous mappers are provided in a single monolithic vlsi device using sub-micron cmos technology. powered from a single +5.0 volt supply, the device dissipates less than one watt typically. the ds1mx7 is provided in a 208-pin plastic quad flat package. its ambient operating temperature range extends from -40 c to 85 c with 0 ft/min airflow. the ds1mx7 device has been designed to meet the latest industry standards, namely: ansi t1.102- 1993 ansi t1.105- 1991 ansi t1.107- 1995 ansi t1.231 (1993 and 1997 draft) ansi t1.403-1995 at&t pub. 62411 (december 1990) bellcore gr-253-core (issue 2) bellcore tr-nwt-000496 (issue 3) bellcore gr-499-core (issue 1) ieee 1149.1- 1990, -1994 itu-t g.707 3-96 itu-t g.783 features that are independently selectable for each of the mappers line interface options meets ansi and bellcore input jitter requirements rail (for asynchronous mapping only) b8zs or ami ansi compliant los detector ansi compliant ais detector 12-bit bpv counters with excessive zeros option nrz option (for asynchronous and byte-synchronous mapping) clock polarity selection for clock in/out nrz data inversion and clock edge options (separate transmit and receive control) for asynchronous use, negative rail can be used to count externally detected code violations programmable clock edges for transmit and receive data external pin per channel for status (may be programmed to combine with internal ais and los to support external loc detector) clock slave for asynchronous input; clock and multiframe synchronization (3 ms), master or slave, for byte-synchronous input separate signaling highway for byte-synchronous, carries abcd signaling bits and ais / yellow alarm information in and out of the ds1mx7 external pin-controlled shut down of all ds1 line drive pins for card protection gapped clock option in place of signaling for 1536 khz datacom in byte-synchronous operation crc-6 generation (ds1 input) and error counting (ds1 output) in byte-synchronous mapping
- 5 of 154 - txc-04201b-mb ed. 4, september 2001 ds1mx7 txc-04201b data sheet proprietary transwitch corporation information for use solely by its customers mapping and synchronizer features mapping to sonet or sdh columns according to gr-253-core or itu g.709 per channel selectable asynchronous and byte-synchronous mapping to a floating vt1.5 or tu-11 for both mapping and demapping overhead assembly with bip-2 calculation, rei-febe (microprocessor or received bip-2 error), signal label (microprocessor value), rdi (microprocessor value or via received signal label mismatch, vt ais, vt lop, or unequipped) and rfi (microprocessor value or ds1 yellow from signaling highway) pointer calculation (fixed at 78 for asynchronous, calculated for byte-synchronous mode) with generated pointer increment and decrement counters (4 bits each) in byte-synchronous mode, line clock may be an input ( ? modified byte-synchronous ? ) or an output ( ? true byte-synchronous ? ) multiplexing of signaling bits from the signaling highway with p 0 /p 1 bit generation unequipped and unassigned vt payload generation vt ais generation (microprocessor value, ais from signaling highway, loss of frame on byte- synchronous, or ais / los / external pin from line decoder) threshold modulator to reduce demapping jitter and wander tracking of input multiframe pulses by pointer movements in byte-synchronous mode demapping and desynchronizer features asynchronous or byte-synchronous per channel, programmable to match mapper mode digital pll with 2 hz low pass filter to track up to + 250 hz nominal ds1 signal providing a smooth clock output with no need for an external de-jitter buffer separate + 5 byte pointer leak buffer with programmable dual slope leak rate (8 ms to 2048 ms per bit in 8 ms steps, automatically doubled to 16 ms to 4096 ms per bit in 16 ms steps within + 12 bits of center of pointer leak buffer) power down with all-zeros or all-ones sent to line interface demapping of sonet or sdh columns according to gr-253-core or itu g.709 asynchronous and byte-synchronous demapping of a floating vt1.5 / tu-11 pointer tracking and extraction of overhead (v5 and z7/k4), lop, ais, ss and ndf with received pointer increment and decrement counters (4 bits each) overhead processing with bip-2 calculation and error counting (12-bit, with overflow), rei (febe) counting (12-bit, with overflow), rdi (1- and 3-bit)/ rfi / signal label de-bouncing and detection, signal label mismatch / unequipped detection de-multiplexing of signaling bits to the signaling highway with multiframe generation for byte- synchronous ds1 ais from microprocessor value, vt ais, vt lop, signal label mismatch or unequipped ds1 yellow to signaling highway from rfi fractional t1 for frame relay, atm aal1 access framer not required for many applications receive and transmit gapped clock (1536 kbit/s) per mapper in byte-synchronous mode crc-6 generation and checking direct connection to multichannel hdlc or atm devices for n x 56 or n x 64 kbit/s service internal dpll to minimize received jitter
- 6 of 154 - txc-04201b-mb ed. 4, september 2001 proprietary transwitch corporation information for use solely by its customers ds1mx7 txc-04201b data sheet signaling support for byte-synchronous mapping receive and transmit temporary buffers to align vt1.5/tu-11 payloads to signaling highway signaling bits mapped to and demapped from specific locations per gr-253-core and g.709 a, ab, abcd signaling bit support byte synchronous operation with transwitch qt1f- plus vlsi device: signaling bit positions in received ds0s optionally replaced with ones by qt1f- plus vt ais and vt rfi to ds1 ais and ds1 rai (yellow) respectively ds1 ais and ds1 rai (yellow) to vt ais and vt rfi respectively unicode support (ds0 alarms) for byte-synchronous operation planned in future framers alarms and errors detection of vt ais, vt rfi, unequipped, signal label mismatch, vt loss of pointer, single-bit rdi, 3-bit rdi, and demap error in the demap direction detection of ds1 ais, loss of signal, map error, and external pin alarm, in the mapping direction counting of code violations (with or without excessive zeros) or crc-6 errors, bip-2, rei (febe), pointer generation and receive pointers with presets and overflow indications microprocessor enable and insert of all alarms detected from line, calculated, or in overhead maintenance loopbacks - ds1 line remote (toward ds1 line), ds1 line local (toward telecom bus), and telecom bus (toward ds1 line for all seven channels at once) pbrs generator in transmit framer and analyzer in receive path per t1 channel 2 15 -1 pattern. separate control bits with software indication power-down modes force transmit leads to low, high or tristate microprocessor interface nineteen-bit status register for vt ais, vt rfi, unequipped, signal label mismatch, vt loss of pointer, single-bit rdi, 3-bit rdi, ds1 ais, loss of signal, map error, demap error, external pin alarm, and counter overflow bits for code violation/crc-6, bip-2, rei (febe), pointer generation and receive pointers latched event registers and interrupt mask registers to individually control each condition twelve-bit crc-6 (byte-synchronous)/ code violation (asynchronous), bip-2, and rei (febe) error counters four-bit increment and decrement pointer generation and receive pointer counters shadow registers for all counters full control of alarm mapping through enable bits microprocessor forcing of alarm conditions per channel reset and resynchronization register access to j2, v5, z6/n2, z7/k4 bytes and o-bits for read and write performance and fault monitoring one second basis, via backplane one second clock shadow registers for all 19 alarms and 7 counters separate registers to indicate alarm changes (performance) and hard conditions (faults) are updated every second to simplify performance report generation
- 7 of 154 - txc-04201b-mb ed. 4, september 2001 ds1mx7 txc-04201b data sheet proprietary transwitch corporation information for use solely by its customers features that are only selectable for the seven mappers as a group telecom bus interface single add bus and drop bus with individual timing operation at 6.48 mbyte/s or 19.44 mbyte/s compatible with transwitch sot-1e and sot-3 functional "b" version devices parity generation and detection with device alarm (odd or even) on data and spe / c1j1v1 sonet mapping via vt1.5 at 6.48 and 19.44 mbyte/s sdh mappings via tu-11 to au-3 or to tug-3 at 19.44 mbyte/s uses spe and c1j1v1 to locate individual vts separate sts-1 phases permitted in an sts-3 for asynchronous and modified byte- synchronous operation each transmit and receive time slot is programmable to one of 28 or 84 including internal and external add bus contention monitors with global alarm add bus timing programmable to zero or one clock delay drop or add bus clock edges programmable add bus enable pin plus control pins for optional poh and/or toh drive per vt/ tu signal failure input via common pin clock and spe / c1j1v1 presence detectors on system in and system out buses, which generate device alarms on failure external line interface transceiver support three-wire serial port to read/write control up to seven line interface transceivers ( ? host mode ? ) designed to support integrated microprocessor control of loopbacks, alarms and line build out per channel or broadcast for data out internal registers to drive and read external devices common microprocessor support microprocessor global reset, masks, polling registers, interrupt polarity and latch edge control motorola split address/data or intel split address/data global alarm indications ( ? or ? of per channel alarms of the same type) with a channel pointer register indicating channels with any active alarms global interrupt mask bits, one per alarm type interrupt on alarm changes: on positive edge, negative edge or both edges device level alarms for telecom bus signals and reference clocks using status and latched event registers with interrupt mask registers device level alarms can be enabled to appear on separate interrupt line for card protection via hardware or software mechanisms error insertion via the microprocessor for parity testing on the telecom bus timed error insertion for rei (febe) and bip-2 global value hardware interrupt polarity selection common hardware reset pin and global software reset register
- 8 of 154 - txc-04201b-mb ed. 4, september 2001 proprietary transwitch corporation information for use solely by its customers ds1mx7 txc-04201b data sheet auxiliary port common access to or from optional overhead bytes for special purposes with microprocessor enables access to j2, v5, z6/n2, z7/k4 bytes and o-bits received via a shared serial port insertion of j2, z6/n2, z7/k4 bytes and o-bits to mapping direction via a shared serial port ring port common permits rei (febe) and single/three-bit rdi values to be sent from one ds1mx7 to another ushr/p support shared serial port with clock and frame for transmit and receive pair of ds1mx7s provides for dual telecom bus applications protection, test and maintenance support ieee 1149.1 boundary scan ability to tristate all outputs for in-circuit testing with a single control pin loss of clock detectors and parity generator/error detector for add and drop telecom buses internal alarm output programmable to a variety of bus fault and clock fault conditions and a card switch-off feature to assist in implementing protection switching external shadow register clock input (1hz + 32 ppm) prbs generator and analyzer switchable to any of the seven mapper channels
- 9 of 154 - txc-04201b-mb ed. 4, september 2001 ds1mx7 txc-04201b data sheet proprietary transwitch corporation information for use solely by its customers block diagram figure 1. ds1mx7 txc-04201b block diagram input timing decoder rx signaling store rx alarm control output timing coder tx signaling store tx alarm control lrclkn rsyncn rposn rnegn/ rsigln/ rcvn/ laisn ltclkn tsyncn tposn tnegn/ tsigln/ microprocessor interface and common control/status i/o lcsn seli readi/wri wri motoi dtb (0-7) addr (0-8) rdyo/ dtacko into/ irqo serial port control tel bus out ctl tel bus in ctl synchronizer/ mapper clk,mf abcd, fr clk,mf ais, rfi abcd, fr data data lo, srclk 7 1 test mapper timing telecom bus inter- 8 inc./dec. & alarms slot timing clk,spe, alarm & control data 8 data slot timing c1j1v1, clk,spe apar aadd aclk ac1j1v1 aspe ad(0-7) daten buschk dclk dc1j1v1 dspe dd(0-7) dfail master dpar 8 tck tdo trs tdi tms 8 9 lsclk lsdo lsdi lo, srclk 8 prbs gen. & anal. t1si pcki highz ais,yel & rei (febe) configi 3 c1j1v1 8 vt termination block ais, rfi from prbs gen iao tsta tstb to prbs an trib. lpbk facility loopback rsti desynchronizer/ demapper ais los cso note: n=1-7 6 face (channel blocks) t a p * marks the eight parts of the line interface block. 6 * * * * * * * * 6 6 telecom bus side tributary side system side line side channel block #1 access port (boundary scan) interface interface auxiliary port ring port oapcko oapado oapdvo oapdto iapcko oapavo orpcko orpdto irpcki irpfmi irpdti orpfmo iapavo iapado iapdvo iapdti tgcon rgcon 6 readi /
- 10 of 154 - txc-04201b-mb ed. 4, september 2001 proprietary transwitch corporation information for use solely by its customers ds1mx7 txc-04201b data sheet block diagram description a simplified block diagram of the ds1mx7 device is shown in figure 1. the major blocks are the seven chan- nel blocks, the microprocessor interface, the serial port control interface, the ring port, the auxiliary port, the prbs (pseudo-random binary sequence) generator and analyzer, the test access port interface, the map- per timing block and the telecom bus interface. each of the seven channel blocks consists of the following component blocks: decoder/coder and input/output timing (for receive and transmit line interfaces), receive and transmit alarm control, receive and transmit signaling store, synchronizer/ mapper and desynchronizer/ demapper, vt termination, and telecom bus input and output control blocks. the receive and transmit line interface blocks connect each of the seven mapper channels to an external line interface transceiver, which performs the liu and clock recovery functions for the asynchronous mode of oper- ation. the interface to the transceiver can be configured for two interface modes: a dual unipolar (rail) interface or a nrz interface. when the byte-synchronous mode of operation is used, the clock and synchronization sig- nals to and from an external ds1 framer are handled by these blocks; data is always in the nrz mode. these blocks also provide a tributary (transmit to receive) loopback and a facility or remote (receive line to transmit line) loopback. when the dual unipolar interface mode is selected, input data from the external line interface transceiver is clocked into the ds1mx7 on pins rposn and rnegn using the recovered receive clock present on the lrclkn input pins, where n=1-7 identifies one of the seven mappers (note: rnegn is one of several pins that has multiple functions, with a signal symbol for each). in the transmit direction, unipolar data is clocked out of the ds1mx7 on pins tposn and tnegn by the transmit line clock present on the ltclkn output pins. global control bits are provided in the memory map which enable the unipolar data to be clocked in and out of the ds1mx7 on either edge of the clocks. for the dual unipolar interface mode, the ds1mx7 provides either a bipolar with eight zero substitution (b8zs), or an alternate mark inversion (ami), coder and decoder function, and loss of signal detection. the loss of signal detector meets the requirements specified in the ansi t1.231 document listed above in the ds1mx7 features section. an unframed ais detector is also provided to assist in network fault isolation. a 12-bit performance counter is provided for each mapper, for counting b8zs coding violation errors. an option is provided to also include excessive zeros in the coding violations counter. when the nrz interface mode is selected and the mapper channel is programmed for asynchronous mapping, nrz data is clocked in at the rposn pin by the recovered received clock input on the lrclkn pin. the nrz data is clocked out of the ds1mx7 on the tposn pins by the transmit system clock present on the ltclkn pins. global control bits are provided in the memory map which enable the nrz data to be inverted or clocked in and out of the ds1mx7 on either edge of the clocks. bipolar violations which are detected in the external line interface transceiver may be clocked into the ds1mx7 on the rnegn/rcvn pins and counted in the associ- ated 12-bit coding violation performance counter. the tnegn output may be used in nrz mode as a spare drive bit. the remote line loopback function for each framer is also implemented in the line interface blocks. when the nrz interface mode is selected and the mapper channel is programmed for byte-synchronous map- ping, nrz data is clocked in at the rposn pins by the clock present on pins lrclkn. the ds1mx7 can gen- erate a clock on lrclkn and a 3.0 ms multiframe synchronization signal on pins rsyncn if an external slip buffer is provided in the framer or if the source of the signal is a clock slaved to the ds1mx7. if lrclkn and rsyncn are inputs, the ds1mx7 translates any clock phase movements with respect to the sonet/sdh clock via vt/tu pointer movements. for applications that do not require a framer but where the ds1 esf crc-6 performance monitoring function is desired (true byte-synchronous mode only), the ds1mx7 calcu- lates and inserts crc-6 into the defined frame bit positions in the vt1.5/ tu-11 structure in the mapping direc- tion. after demapping, the crc-6 is checked and any errors found are counted in the 12-bit counter shared for code violation counting. byte-synchronous mapping supports the independent transmission of signaling through defined nibbles in the vt1.5/ tu-11 structure, as shown in figure 2. the ds1mx7 provides receive and transmit signaling stores to synchronize signaling and framing bits to and from a ds1 framer or switching stage with the mapper and
- 11 of 154 - txc-04201b-mb ed. 4, september 2001 ds1mx7 txc-04201b data sheet proprietary transwitch corporation information for use solely by its customers demapper blocks. signaling is received through the rnegn/rsigln pins in byte-synchronous mode, being clocked in with lrclkn. signaling is sent out on the tnegn/tsigln pins in byte-synchronous mode, using ltclkn. transwitch framers like the qt1f- plus (txc-03103) can utilize the signaling bits on the signaling highways for automatic signaling propagation between sonet/sdh byte-synchronous mapping and ds1 lines. for applications using the full ds1 payload in byte-synchronous mode, the rnegn/rsigln pins can be programmed to supply gapped clock (rgcon), as can the tnegn/tsigln pins (tgcon). the receive and transmit alarm control blocks work in conjunction with the receive and transmit line inter- face blocks as well as the receive and transmit signaling store blocks to move ds1 alarm signals in and out of the ds1mx7. the receive alarm control block detects specific bits from the receive signaling highway, such as ais or rai (yellow), for forwarding to the mapper block as ais and rfi. it also gathers los and ais from the receive line interface. the laisn input pin may be used for forwarding an externally detected loss of sig- nal or loss of clock, or as a general interrupt input. the transmit alarm control block translates rfi and ais from the demapper block along with microprocessor controls to set specific bits on the transmit signaling high- way. transwitch framers like the qt1f- plus (txc-03103) can utilize the control bits on the signaling highways for automatic alarm propagation between sonet/sdh and ds1 lines. for card protection schemes, control input pin cso , when driven low, causes all of the output pins for the seven line interfaces to go low. the synchronizer/ mapper block takes the clock and data from the receive line interface in asynchronous mode, threshold modulates it with srclk, buffers it in a fifo and inserts the data bits in the information bit positions of the asynchronous vt1.5/ tu-11, and stuffs it using the two stuff opportunity bits with indication in the c1 and c2 bits, as shown in figure 2. the stuffing matches the received ds1 clock to the bit positions available based on the sonet/sdh network clock supplied to the ds1mx7 in the add telecom bus clock, aclk and the ac1j1v1 signal. optional overhead bytes j2, z6/n2, o and part of z7 are taken from micropro- cessor-written values or the auxiliary port. the synchronizer/ mapper block takes the clock, frame and data from the receive line interface in byte-syn- chronous mode, buffers it in a fifo and writes it to defined byte positions in the byte-synchronous vt1.5/ tu-11 along with the optional overhead bytes j2, z6/n2 and part of z7 which are taken from microprocessor- written values or the auxiliary port. for byte-synchronous mode the signaling bits are taken from the receive signaling store and mapped to the correct positions in the vt1.5/ tu-11. the 500-microsecond long vt superframe shown in figure 2 is repeated six times, being synchronized to the rsyncn 3.0 millisecond input. the p 1 p 0 bits are generated to indicate which signaling bits are being carried in a specific vt superframe and are related to rsyncn. fifo conditions are monitored and can lead to increment or decrement requests of the vt termination block. synchronization changes in rsyncn are monitored for possible ndf requests. the vt termination block takes the mapped data and optional overhead together with any frame, increment or decrement indications associated with byte-synchronous mode from the synchronizer/ mapper block. the v5 and z7 bytes are built from one of several received ds1 alarm sources (the receive alarms, ring port error conditions, or microprocessor-written values). parity is then calculated over the payload. v1 and v2 are set to 78, positioning v5 just after v1 for asynchronous mode only. for byte-synchronous mode (true byte-synchro- nous or modified byte-synchronous), the v1 and v2 bytes are generated to track the phase of the incoming ds1 signal relative to aclk; two four-bit counters are provided to keep track of pointer increments and pointer decrements generated. if a new position for the rsyncn pulse is generated, this block will generate an ndf along with the new pointer. if the ds1mx7 acts as a clock source, the lo pin will be used to provide this clock and it must be frequency locked to the sts-1 or stm-1 clock, or pointer justifications and/or mapping errors will result. if ais is to be generated the entire payload is ones. if unassigned (idle) is to be generated, an all- zeros payload with a valid v5 is generated. if an unequipped is to be generated, an all-zeros payload including v5 is generated. the vt termination block also provides the pointer tracking, v5 and z7 overhead location and vt1.5/ tu-11 alarm detection and de-bouncing functions. the alarms (rdi in four flavors, rfi, unequipped, signal label mismatch, lop, ais, rei, bip-2 errors, etc.) are made available to the common microprocessor block for latch- ing, shadowing, counting and interrupting purposes. alarms are provided on the ring port for rdi and rei to support ring applications. it also identifies the payload for the desynchronizer/ demapper block as well as any pointer movements.
- 12 of 154 - txc-04201b-mb ed. 4, september 2001 proprietary transwitch corporation information for use solely by its customers ds1mx7 txc-04201b data sheet a normal ndf is shown (new data flag = 1001); s1s2 = 11; positive justification = invert the 5 i-bits; negative justification = invert the 5 d-bits; shown msb (bit 1) first. shown msb (bit 1) first. rei-v is also known as febe. rdi-v set to a 1 for unequipped, ais-v and lop-v. 3-bit rdi-v codes: 001 = no defects; 010 = signal label mismatch; 101 = ais-v or lop-v; 110 = unequipped. figure 2. vt1.5/ tu-11 asynchronous and byte-synchronous mappings byte-synchronous floating vt mode legend: asynchronous floating vt mode v 1 c n = stuff control v 1 v 5 f = ds1 frame bit v 5 p 1 p 0 s 1 s 2 s 3 s 4 f r i = information r r r r r r i r ds0 channels 1 - 24 j 2 = vt path trace 24 information bytes v 2 o = overhead bits v 2 j 2 p 1 p 0 = signaling phase j 2 p 1 p 0 s 1 s 2 s 3 s 4 f r r = fixed stuff c 1 c 2 o o o o i r ds0 channels 1 - 24 s n = signaling 24 information bytes v 3 st n = stuff opportunity v 3 z 6 v 1 and v 2 = pointer z 6 p 1 p 0 s 1 s 2 s 3 s 4 f r v 3 = inc/dec opportunity c 1 c 2 o o o o i r ds0 channels 1 - 24 24 information bytes v 4 v 4 = unused v 4 z 7 v 5 = vt overhead z 7 p 1 p 0 s 1 s 2 s 3 s 4 f r z 6 = reserved byte c 1 c 2 r r r st 1 st 2 r ds0 channels 1 - 24 z 7 = reserved and 3-bit rdi byte 24 information bytes v1 byte v2 byte new data flag size ididididid 0110s1s2 pointer range = 0 - 103 decimal 1v5 byte8 bip-2 rei-v rfi-v signal label rdi-v 1z7 byte8 rrrr 3-bit rdi-v r
- 13 of 154 - txc-04201b-mb ed. 4, september 2001 ds1mx7 txc-04201b data sheet proprietary transwitch corporation information for use solely by its customers the desynchronizer/ demapper block takes the data and alarm information, along with pointer information, and extracts the ds1 signal. this block extracts the optional overhead bytes and sends v5, z6/n2, o and z7/ k4 to the auxiliary port for asynchronous mode. for byte-synchronous mode, the o bytes are omitted and the signaling bits are sent to the transmit signaling store instead. in both modes the data is sent to a pointer leak buffer which is programmable for leak out rate. this is used to minimize jitter and wander on asynchronously mapped signals as well as to smooth out byte-synchronously mapped signals that utilize pointer movements for frequency adjustment. the pointer leak rate may be adjusted to meet mtie requirements with a simple soft- ware algorithm which uses the one second latched pointer increment and decrement counters. the desyn- chronizer uses a dpll operated from the signal on srclk (48.636 mhz) that smooths out the stuffing jitter and compensates for the demapping gapped positions used for all orders of overhead. the desynchronizer outputs a ds1 clock along with the ds1 data to the transmit line interface block ready for transmission or framing without additional de-jittering. in byte-synchronous mode the frame pulse (3.0 ms) is decoded from the p 1 p 0 bits and is used to align the signaling highway to the transmit signaling store, and it becomes the signal on tsyncn. a correct p 1 p 0 pattern must be supplied for proper operation even if signaling is not used. alarm information (rfi and ais) is sent to the transmit alarm block for forwarding on the signaling highway. ais is used to cause the dpll to output an in-frequency-range all-ones signal. the telecom bus input and output control blocks buffer the assembled vt1.5/ tu-11 bytes for insertion to or extraction from the telecom bus interface. each of the seven mapper channels can independently be placed on or independently taken from any one of three sts-1s or tug-3s (19.44 mhz telecom bus only), any one of seven vt groups or tug-2s, and any one of four vt1.5 or tu-11s. enable control bits allow a channel to be disconnected in transmit and/or receive from the telecom bus. the telecom bus interface block combines the signals from the seven mapper channels and synchronizes them to the add bus half of the telecom bus based on the aclk, ac1j1v1 and aspe signals. it can be con- figured as a single sts-1 (6.48 mhz), an sts-3 (19.44 mhz) or an stm-1 (19.44 mhz). contention checks are made for the seven mapper channels; this feature is extended using the buschk pins to up to 3 additional ds1mx7 devices sharing an add bus. parity (pin apar) and an add indication (pin aadd ) are included with the byte-wide data (pins ad(0-7)). the daten and master pins allow optional drive of overhead and stuff columns, when the data delay option is not used. the drop bus part of the telecom bus provides dclk, dc1j1v1 and dspe signals along with a failure indication (pin dfail) to indicate to the seven mapper chan- nels that the received data is errored due to higher order path, section or line failures. parity (pin dpar) is included with the data (pins dd(0-7)). parity covers add and drop data and optionally spe and c1j1v1 sig- nals. all signals are monitored for failure and maskable interrupts may be generated both to the microproces- sor interrupt pin and to a separate failure pin (iao ). the ds1mx7 has a prbs generator and analyzer block. the generator and analyzer supports the 2 15 -1 pat- tern. the generator output may be substituted in place of the nrz data stream output from each receive line interface decoder. the analyzer monitors one of the nrz data stream outputs from the seven receive line interface decoders. by setting the telecom bus loopback (a function of the telecom bus interface block) and a tributary loopback for one of the seven channels, the entire channel ? s transmit and receive path can be veri- fied (synchronizer/ mapper, vt termination, telecom bus interface, desynchronizer/ demapper, transmit line interface and receive line interface). by moving the loopbacks to framers, lius, vt switches or remote end mappers an entire path can be verified. the line interface control block is a common block to all seven mapper channels that provides a serial port for communicating with an external line interface transceiver that supports ? host mode ? operation. this allows the system microprocessor to control the transceiver through the ds1mx7. the interface consists of a data output pin (lsdo), clock output pin (lsclk), and a data input pin (lsdi). these signals are shared between all of the transceivers. each transceiver is selected by the ds1mx7, using chip select output signals (lcsn ). in addition, a general purpose input pin (laisn) can be used in nrz mode to generate a maskable interrupt.
- 14 of 154 - txc-04201b-mb ed. 4, september 2001 proprietary transwitch corporation information for use solely by its customers ds1mx7 txc-04201b data sheet the test access port block is common to all seven mapper channels and includes a five-pin test access port (tap) that conforms to the ieee 1149.1 standard. this block provides external boundary scan to read and write the ds1mx7 input and output pins from the tap for board and component testing. in addition, a four-byte read only memory location is provided for reading the jedec manufacturer id, ds1mx7 part number, and ver- sion number of the part. for non-boundary scan testing a highz pin is provided to tristate all output pins. the ds1mx7 provides a common six-wire ring port block. a pair of ds1mx7 devices can operate on a dual bus-based add drop multiplexer. since each ds1mx7 is configured to operate in a single one direction of the ring, rdi and rei (febe) values need to be sent to the mate ds1mx7 so that they are returned in the oppo- site direction. the ring port is shared among the seven mapper channels to facilitate the function of sending, receiving and buffering rei (febe) and rdi values from and for each of the seven mapper channels. the rei (febe) and rdi information used by the mapper may either come from the demap direction within the ds1mx7 (non-ring mode), from a microprocessor-forced value, or from the ring port. the ring port outputs clock, data and frame (pins orpcko, orpdto and orpfmo), and it expects clock, data and frame as inputs (pins irpcki, irpdti and irpfmi). a common auxiliary port block is provided that makes the optional and reserved overhead bytes to and from each of the seven mapper channels available on multiplexed ds1mx7 device pins. the auxiliary port outputs the v5, j2, z6/n2, z7/k4 and o bytes as they arrive, if enabled. when mapping opportunities for j2, z6/n2, z7/k4 and o bytes come up the auxiliary port requests and inputs these bytes, if enabled. microprocessor read and write access of these bytes is also provided. the ds1mx7 can be configured to operate with either intel or motorola-compatible microprocessors via the microprocessor input/output interface block. separate address, data and control pins are provided. interrupt capability is provided with global and individual framer mask bits as well as activity registers to guide software to the exact cause of an interrupt in the most expeditious manner. a wide variety of alarms is provided on a glo- bal level as well as on a per mapper channel level. each alarm or error is reflected in a current status register or counter as well as a latched value register that may be set on the rising, falling or both edges of an alarm. shadow registers for alarms and counters are provided, with the alarm shadow registers doubled to indicate either a change (performance item) or a persistent condition (fault). any latched value may trigger an interrupt, unless it is masked to prevent it causing an interrupt. an option is provided in software which permits the inter- rupt polarity to be inverted. an external system clock provided at pin pcki is used to run the internal state machines.
- 15 of 154 - txc-04201b-mb ed. 4, september 2001 ds1mx7 txc-04201b data sheet proprietary transwitch corporation information for use solely by its customers pin diagram figure 3. ds1mx7 txc-04201b pin diagram rsync5 tpos5 lcs5 vdd lrclk6 nc rsync6 tpos6 tsync6 lcs6 rpos7 vdd nc rsync7 tpos7 gnd irpfmi irpdti lt c l k 5 irpcki gnd orpdto tsync5 rpos6 lais6 lt c l k 6 gnd lais7 lrclk7 orpfmo lt c l k 7 vdd tsync7 orpcko lcs7 35 55 50 45 40 5 125 130 135 140 145 150 155 10 15 20 25 30 1 75 70 80 120 115 110 105 100 95 90 85 65 60 ds1mx7 (top view) 200 180 185 175 160 165 170 190 195 205 tdi tdo trs tms nc gnd t1si iao srclk nc tck vdd tsta tstb addr0 vdd addr4 nc addr5 addr6 addr7 dtb0 dtb1 dtb3 vdd dtb4 nc nc dtb6 gnd wri pcki highz rsti motoi gnd nc cso addr3 addr2 addr1 addr8 gnd dtb2 dtb5 dtb7 seli rdyo/dtacko vdd into/irqo readi / readi/wri nc iapdti iapdvo iapavo iapado oapcko gnd oapdto oapdvo oapavo iapcko oapado vdd lrclk1 rneg1/rsigl1/ lo lsclk gnd lsdi lsdo buschk2 buschk1 ad0 ad1 ad3 ad4 gnd ad5 ad7 nc aclk dc1j1v1 nc rpos1 nc dspe lais1 dfail vdd configi daten master vdd buschk0 ad2 ad6 vdd gnd aadd apar nc aspe ac1j1v1 dd1 dd2 dd0 dpar vdd dclk dd6 dd7 dd5 dd4 gnd dd3 lrclk5 rneg5/rsigl5/rcv5/rgco5 lcs4 tpos4 gnd rsync4 lrclk4 rneg4/rsigl4/rcv4/rgco4 nc lais4 lcs3 lt c l k 3 tneg3/tsigl3/tgco3 gnd tpos3 lrclk3 nc rneg3/rsigl3/rcv3/rgco3 rsync2 nc rpos5 nc tpos2 lais5 tneg2/tsigl2/tgco2 vdd tneg4/tsigl4/tgco4 lt c l k 4 tsync4 vdd rpos4 tsync3 rsync3 vdd gnd rpos3 lt c l k 2 lais3 tsync2 lcs2 lais2 lcs1 rpos2 rneg2/rsigl2/rcv2/rgco2 vdd lrclk2 tpos1 rsync1 tneg1/tsigl1/tgco1 lt c l k 1 gnd tsync1 tneg6/tsigl6/tgco6 rneg7/rsigl7/rcv7/rgco7 tneg5/tsigl5/tgco5 rneg6/rsigl6/rcv6/rgco6 tneg7/tsigl7/tgco7 rcv1/rgco1
- 16 of 154 - txc-04201b-mb ed. 4, september 2001 proprietary transwitch corporation information for use solely by its customers ds1mx7 txc-04201b data sheet pin descriptions power supply and ground *note: i = input; o = output; p = power; t = tristate per channel tributary i/o (n = 1 to 7) symbol pin no. i/o/p* type name/function vdd 11, 23, 35, 47, 63, 75, 87, 99, 115, 127, 139, 151, 167, 179, 191, 203 p vdd: +5 volt supply, 5% gnd 5, 17, 29, 41, 57, 69, 81, 93, 109, 121, 133, 145, 161, 173, 185, 197 p gnd: ground nc 13, 25, 27, 33, 37, 65, 73, 77, 101, 117, 129, 141, 153, 169, 181, 198, 205 nc: not connected. leave floating. do not make any external connections to these pins or connect them to one another. connection may impair perfor- mance or cause damage to the device. symbol pin no. i/o/p type * name/function lrclkn 104, 116, 130, 143, 156, 168, 182 i/o cmos line receive clock input: 1.544 mhz 200 hz clock from dsx-1 receiver for asynchronous mapping mode; (tolerance is 50 hz per ansi and bellcore for byte- synchronous operation). global control bit rcae (bit 6) in register 007h determines the active edge of this clock. input jitter tolerance is 5 ui peak to peak from 10 hz to 500 hz and 0.1 ui peak to peak from 8 khz to 40 khz. see bellcore tr-tsy-000499. for byte-synchronous operation with an external slip buffer for which control bits mode1,0 (bits 1 and 0) in register x+00h are set to 10, lrclkn is an output derived from pin lo. rsyncn 105, 118, 131, 144, 157, 170, 183 i/o cmos receive frame sync.: 3.0 millisecond multi-frame sync from framer, or to framer for byte-synchronous mode. sampled on lrclkn falling edge if global control bit rcae (bit 6) in register 007h is set to a 0. for byte-synchronous operation with an external slip buffer for which control bits mode1,0 (bits 1 and 0) in register x+00h are set to 10, rsyncn is an output derived from pin lo. rposn 102, 113, 126, 140, 154, 165, 178 icmos tributary receive data (positive): nrz/positive rail. ds1 data from framer or dsx-1 receiver. rposn is sampled on lrclkn falling edge if global control bit rcae (bit 6) in register 007h is set to a 0. in nrz mode, global control bit rxnrzp (bit 4) in register 007 selects the polarity (a 1 selects a low as a logical one). *note: see input, output and input/output parameters section below for type definitions.
- 17 of 154 - txc-04201b-mb ed. 4, september 2001 ds1mx7 txc-04201b data sheet proprietary transwitch corporation information for use solely by its customers rnegn/ 103, 114, 128, 142, 155, 166, 180 i/o cmos tributary receive data (negative): negative rail ds1 data from dsx-1 receiver. this pin is sampled on lrclkn falling edge if global control bit rcae (bit 6) in register 007h is set to a 0. rsigln/ receive signaling highway input: signaling highway from framer. sampled on lrclkn falling edge if global control bit rcae (bit 6) in register 007h is set to a 0. rcvn tributary receive code violations: code violation counter input. sampled on lrclkn falling edge if global control bit rcae(bit 6) in register 007h is set to a 0. rgcon receive gapped clock output: when the datacom mode is selected (only available for byte-synchronous operation) via control bit datacom (bit 5) in per channel register x+00h being set to a 1, this pin provides a gapped clock output in which the gap appears at the frame bit times on rposn. laisn 100, 112, 125, 138, 152, 164, 177 icmos line alarm input: line transceiver interrupt, ais or loss of signal / clock from dsx-1 receiver.the active level is determined by global control bit rxnrzp (bit 4) in register 007, which selects the polarity (a 1 selects a low as a logical one). a per channel control bit explos (bit 6) in register x+00h enables this pin to act as los if set to a 1. control bit los2ais (bit 6) in register x+01h, when set to a 1, causes this signal to propagate vt ais upstream. when explos is set to a 0, status bit xps (bit 7) in register x+10h becomes a separate status indi- cation with latched, mask, performance and fault regis- ters plus global mask and status capability. ltclkn 108, 122, 135, 148, 160, 174, 187 ocmos line transmit clock output: 1.544 mhz 200 hz clock to dsx-1 line driver or framer. global control bit tcae (bit 7) in register 007h determines the active edge of this clock. see cso below. the output fre- quency tracks the input frequency as defined by the syn- chronized payload. output jitter caused by de- synchronization and single pointer movements is 0.4 ui or less peak to peak at 10 hz and above (0.075 ui peak to peak or less from 8 khz to 40 khz). tposn 106, 119, 132, 146, 158, 171, 184 ocmos tributary transmit data (positive): nrz/positive ds1 data to dsx-1 line driver or framer. output on ltclkn rising edge if global control bit tcae (bit 7) in register 007h is set to a 1. in nrz mode, global control bit txnrzp (bit 0) in register 007h selects the polarity (a 1 selects a low as a logical one). also see cso below. symbol pin no. i/o/p type * name/function
- 18 of 154 - txc-04201b-mb ed. 4, september 2001 proprietary transwitch corporation information for use solely by its customers ds1mx7 txc-04201b data sheet tributary common control tnegn/ 107, 120, 134, 147, 159, 172, 186 ocmos tributary transmit data (negative): negative rail ds1 data to dsx-1 line driver output on ltclkn rising edge if global control bit tcae (bit 7) in register 007h is set to a 1. when nrz mode is used in asynchronous mode this pin can be used as a spare output (e.g., select b8zs/ami in line i/f transceiver). also see cso below. tsigln transmit signaling highway output: signaling high- way to framer. output on ltclkn rising edge if global control bit tcae (bit 7) in register 007h is set to a 1. also see cso below. tgcon transmit gapped clock output: when the datacom mode is selected (only available for byte-synchronous operation) via control bit datacom (bit 5) in per channel register x+00h being set o a 1, this pin provides a gapped clock output in which the gap appears at the frame bit times on tposn. tsyncn 110, 123, 136, 149, 162, 175, 188 ocmos transmit frame sync: 3.0 millisecond multi-frame sync to framer. output on ltclkn rising edge if global control bit tcae (bit 7) in register 007h is set to a 1. also see cso below. lcsn 111, 124, 137, 150, 163, 176, 189 ocmos line interface transceiver chip select: an active low signal that enables communications in both directions between the external line interface transceiver for chan- nel n and the ds1mx7. this pin is under control of glo- bal register 01ah where ensrp (bit 4) enables transmission to channel n, which is selected by bdcst (bit 7) to select all channels or the channel selection controls (bits 2-0) which select one of the 7 channels. symbol pin no. i/o/p type name/function lo 98 i cmos local oscillator: 1.544 mhz 32 ppm system clock input used for byte-synchronous mode. 1.544 mhz syn- chronized to system (aspe, aclk and a specific j1 of ac1j1v1) for byte-synchronous operation where lrclkn and rsyncn are outputs. this signal is also used to generate the serial port clock output lsclk. srclk 206 i cmos system reference clock: 48.636 mhz 32 ppm (31.5 times 1.544 mhz) system clock input used to operate the synchronizer, desynchronizer, prbs generator/ ana- lyzer, and to generate ds1 ais. symbol pin no. i/o/p type * name/function
- 19 of 154 - txc-04201b-mb ed. 4, september 2001 ds1mx7 txc-04201b data sheet proprietary transwitch corporation information for use solely by its customers lsdo 91 o cmos line interface transceiver data output signal: com- mon serial control data bus output shared by the seven channels. a command byte followed by a data byte, as stored in control registers 017h and 018h respectively, is transmitted to the line interface transceiver selected by lcsn . lsdi 92 i cmos line interface transceiver data input signal: com- mon serial control data bus input. a data byte coincident with the data byte on lsdo is clocked into the ds1mx7 and stored in register 019h from the line interface trans- ceiver selected by lcsn . lsclk 94 o cmos line interface transceiver clock signal: common serial control bus clock output. a 1.544 mhz clock derived from lo. lsdo is clocked out of the ds1mx7 on the falling edge of lsclk and lsdi is clocked into the ds1mx7 on the rising edge of lsclk. t1si 207 i ttl one second performance clock input: shadow regis- ter latch. this input operates the latched counters and pm/fm registers. the following parameter value limits are suggested to prevent counters from overflowing when operating in noisy environments or other unfavor- able conditions: min. high time 0.50 ms; min. low time 3.0 ms; max. low time 1.5 s. operation at 1.0 hz + 32 ppm, 1.0 ms high time, is recommended. this clock is used in conjunction with global control bit enpmfm (bit 3) in register 006h to clear per channel event registers (not device event registers) after the pm and fm regis- ters have been updated. iao 208 o cmos open drain (4 ma) internal alarm output: internal alarm detected, active low output. control bits in registers 01bh and 01ch, if set to a 1, enable telecom bus clock, payload and synch. failures, as well as parity errors and prbs out of lock, to generate an alarm or interrupt on this pin. cso 6 i ttl card switch off: when driven low, ltclkn, tposn, tnegn/tsigln and tsyncn are driven to a logic low level. symbol pin no. i/o/p type name/function
- 20 of 154 - txc-04201b-mb ed. 4, september 2001 proprietary transwitch corporation information for use solely by its customers ds1mx7 txc-04201b data sheet system interface symbol pin no. i/o/p type name/function dclk 64 i ttl drop bus clock: telecom bus clock for data from sys- tem; 6.48 mhz for pin configi tied high or 19.44 mhz for pin configi tied low. control bit tbrci (bit 4) in reg- ister 01eh set to a 0 selects the rising edge of dclk as the active edge. dc1j1v1 66 i ttl drop bus c1j1v1 indicator: telecom bus c1#1, j1#1, or v1#1 valid from system. valid on the rising edge of dclk when control bit tbrci (bit 4) in register 01eh is set to a 0. used with dspe to identify the start of the payload. dspe 67 i ttl drop bus spe indicator: telecom bus spe valid from system. valid on rising edge of dclk when control bit tbrci (bit 4) in register 01eh is set to a 0. this signal is high during all vt1.5 or tu-11 bytes from the system. dd(0-7) 61, 60, 59, 58, 56, 55, 54, 53 i ttl drop bus data: telecom bus data from system; dd0 is lsb. valid on rising edge of dclk when control bit tbrci (bit 4) in register 01eh is set to a 0. dpar 62 i ttl drop bus parity bit: telecom bus parity received over dd(0-7), dspe and dc1j1v1. valid on rising edge of dclk when control bit tbrci (bit 4) in register 01eh is set to a 0; odd/even selectable by control bit tbpe (bit 2) in register 007h; when set to a 1, even parity is selected. when control bit tbpis (bit 3) in register 007h is set to a 0 only dd(0-7) is checked for parity. dfail 68 i ttl drop bus signal fail: signal fail indication valid on the rising edge of dclk when control bit tbrci (bit 4) in register 01eh is set to a 0. if dfail is high the specific vt slot contains invalid data (dd(0-7)); the per vt alarms are invalid and are masked; ds1 ais is gener- ated. aclk 76 i ttl add bus clock: telecom bus clock for data to system; 19.44 mhz for pin configi tied high or 6.48 mhz for pin configi tied low. when control bit tbtci (register 01eh, bit 5) is set to a 0, the aspe and ac1j1v1 sig- nals are clocked in on the rising edge of aclk. the fall- ing edge of aclk is used to clock the ad(0-7), apar and aadd signals out to the add bus so that these sig- nals can be sampled on the next rising edge. when tbtci = 1 the opposite clock edges are used. ac1j1v1 72 i ttl add bus c1j1v1 indicator: telecom bus c1#1, j1#1, v1#1 valid for data to system. this signal is sampled on the rising edge of aclk when control bit tbtci (register 01eh, bit 5) is set to a 0. used with aspe to indicate the start of the payload to the system.
- 21 of 154 - txc-04201b-mb ed. 4, september 2001 ds1mx7 txc-04201b data sheet proprietary transwitch corporation information for use solely by its customers aspe 71 i ttl add bus spe indicator: telecom bus spe valid for data to system. this signal is sampled on the rising edge of aclk when control bit tbtci (register 01eh, bit 5) is set to a 0. this signal is high during all vt1.5 or tu-11 bytes to the system. ad(0-7) 86, 85, 84, 83, 82, 80, 79, 78 o(t) ttl 4ma add bus data: telecom bus data to system; ad0 is lsb. the ds1mx7 will output the data on the falling edge of aclk when control bit tbtci (register 01eh, bit 5) is set to a 0. control bit tbdd (bit 3) in register 01eh selects zero aclk clock period delay if set to a 0 and a single aclk clock period delay if set to a 1. these sig- nals are in the tristate condition when the ds1mx7 is not driving the add bus. apar 70 o(t) ttl 4ma add bus parity bit: telecom bus parity generated for any ad(0-7), aspe and ac1j1v1 placed on the tele- com bus. the ds1mx7 will output parity on the falling edge of aclk when control bit tbtci (register 01eh, bit 5) is set to a 0. control bit tbpe (register 007h, bit 2) selects odd/even parity. when tbpe is set to a 0, odd parity is selected. when control bit tbpis (bit 3) in regis- ter 007h is set to a 0 only ad(0-7) is included in the par- ity calculation. control bit tbdd (bit 3) in register 01eh selects zero aclk clock period delay if set to a 0 and a single aclk clock period delay if set to a 1. this signal is in the tristate condition when the ds1mx7 is not driv- ing the add bus. aadd 74 o ttl 4ma add bus add data present indicator: te l e c o m b u s device outputs valid. this signal goes low on the falling edge of aclk when control bit tbtci (register 01eh, bit 5) is set to a 0. this signal is active when the ds1mx7 writes to the telecom bus, allowing for external drivers to be used. control bit tbdd (bit 3) in register 01eh selects zero aclk clock period delay if set to a 0 and a single aclk clock period delay if set to a 1. this signal is high when the ds1mx7 is not driving the add bus. buschk (0-2) 88, 89, 90 i ttl add bus check: used to determine if another ds1mx7 on the same telecom bus is driving in the same slot. each buschk input is connected to the aadd of another ds1mx7. if a collision is detected, status bit tbxes (bit 0) in register 00bh is set to a 1. latched value, mask pm, and fm register bits are also supplied. master 97 i ttlp add bus master: when tied to ground, poh and stuff columns are driven to zero on ad(0-7) with correct parity. see the telecom bus operations subsection. daten 96 i ttl add bus data enable: when high, ad(0-7), apar and aadd are enabled. it is normally tied to aspe to float the telecom bus during toh. symbol pin no. i/o/p type name/function
- 22 of 154 - txc-04201b-mb ed. 4, september 2001 proprietary transwitch corporation information for use solely by its customers ds1mx7 txc-04201b data sheet auxiliary port configi 95 i ttl add/drop bus configuration input: configuration of the telecom bus. for configi high, telecom bus is 28 slot/6.48 mhz. for configi low, telecom bus is 84 slot/ 19.44 mhz. symbol pin no. i/o/p type name/function oapcko 42 o cmos output auxiliary port clock: dclk divided by 2 when configi is high. dclk divided by 4 when configi is low. oapavo 50 o cmos output auxiliary port address valid: oapavo is high during the 12 address-bits of oapado. information is clocked out on the falling edge of oapcko. oapado 48 o cmos output auxiliary port address: address information identifying o-bits, v5, j2, z6/n2, or z7/k4 information that will be output on oapdto. information is clocked out on the falling edge of oapcko. oapdvo 52 o cmos output auxiliary port data valid: oapdvo is high during the eight data bits of oapdto. information is clocked out on the falling edge of oapcko. oapdto 51 o cmos output auxiliary port data: this pin provides the data byte specified in the preceding oapado address. infor- mation is clocked out on the falling edge of oapcko. iapcko 49 o cmos input auxiliary port clock: aclk divided by 2 when configi is high. aclk divided by 4 when configi is low. iapavo 44 o cmos input auxiliary port address valid: iapavo is high during the 12 address bits of iapado. information is clocked out on the falling edge of iapcko. iapado 43 o cmos input auxiliary port address: address information identifying o-bits, j2, z6/n2, or z7/k4 information that will be input on iapdti. information is clocked out on the falling edge of iapcko. iapdvo 46 o cmos input auxiliary port data valid: iapdvo is high during the eight data bits of iapdti. information is clocked out on the falling edge of oapcko. iapdti 45 i ttl input auxiliary port data: this pin accepts the data byte specified in the preceding iapado address. infor- mation is clocked in on the second rising edge of iapcko after the rising edge of iapdvo. symbol pin no. i/o/p type name/function
- 23 of 154 - txc-04201b-mb ed. 4, september 2001 ds1mx7 txc-04201b data sheet proprietary transwitch corporation information for use solely by its customers ring port microprocessor interface symbol pin no. i/o/p type name/function orpcko 190 o cmos output ring port clock: burst of 56 clock pulses at 1.944 mbit/s. orpfmo 192 o cmos output ring port frame: active high signal during bit 0 of channel 1. orpfmo is clocked out on the falling edge of orpcko. orpdto 193 o cmos output ring port data: rei-v (febe), rdi-vpd, rdi-vsd, and rdi-vcd data from all seven channels for use in pps ring applications. information is clocked out on the falling edge of orpcko. irpcki 194 i ttl input ring port clock: burst of 56 clock pulses at 1.944 mbit/s. irpfmi 195 i ttl input ring port frame: active high signal during bit 0 of channel 1. irpfmi is clocked on the rising edge of irpcki. irpdti 196 i ttl input ring port data: rei-v (febe), rdi-vpd, rdi-vsd, and rdi-vcd data for all seven channels for use in pps ring applications. information is clocked in on the rising edge of irpcki. symbol pin no. i/o/p type name/function rsti 4 i ttlp hardware reset: device reset. this active low signal will reset all seven ds1 mappers. it should be held low for a minimum of 4 clock periods of pcki. motoi 38 i ttl motorola mode: motorola - intel microprocessor mode select. high selects motorola. low selects intel. dtb(0-7) 19, 20, 21, 22, 24, 26, 28, 30 i/o ttl 8ma data: microprocessor bidirectional, tristate data bus; dtb0 is lsb. addr(0-8) 7, 8, 9, 10, 12, 14, 15, 16, 18 i ttl address bus: microprocessor address bus; addr0 is lsb. seli 36 i ttlp select: microprocessor interface select. a low selects the interface and allows the transfer of information between the ds1mx7 and the microprocessor. readi / readi/wri 34 i ttl read: read or read/write. intel: low to read ds1mx7. motorola: high to read/low to write. wri 39 i ttl write: intel mode only; low to write to ds1mx7.
- 24 of 154 - txc-04201b-mb ed. 4, september 2001 proprietary transwitch corporation information for use solely by its customers ds1mx7 txc-04201b data sheet boundary scan and test port rdyo/ 31 o(t) ttl 8ma ready: intel mode: a high acknowledges that data transfer can take place this cycle. a low indicates wait states. dtacko data transfer acknowledge: motorola mode: a low during read indicates data bus is valid. a low during write indicates data is accepted. into/ 32 o ttl 4ma interrupt: intel mode: if control bit ipol (bit 4) in register 006h is set to a 0, a high indicates an interrupt request to the microproces- sor. irqo interrupt request: motorola mode: if control bit ipol (bit 4) in register 006h is set to a 0, a low indicates an interrupt request to the microprocessor. pcki 40 i ttl processor clock: processor clock input. required for device operation; 8 to 20 mhz. ds1mx7 will continue to pass data on loss of pcki, but microprocessor access will be blocked. symbol pin no. i/o/p type name/function tck 204 i ttl test clock: ieee 1149.1 boundary scan clock input. this clock is used to shift data into tdi on the rising edge and out of tdo on the falling edge. tdi 201 i ttlp test data input: boundary scan data input. serial test instructions and data are clocked into this pin on the ris- ing edge of tck. tdo 202 o(t) ttl 4ma test data output: boundary scan data output. serial data and test instructions are clocked out of this pin on the falling edge of tck. tms 199 i ttlp test mode select: boundary scan test mode select input; sampled by tck rising edge to put ds1mx7 into test mode. trs 200 i ttlp test reset: boundary scan reset input. this pin will asynchronously reset the test access port (tap) con- troller if held low for a minimum duration of 300 ns. this pin is to be held low, asserted low or pulsed low to reset the tap controller on ds1mx7 power-up. highz 3 icmos high impedance select: grounding this pin causes all outputs except tdo to go high impedance but alters no internal registers. tsta 1 icmos test a: device test pin. must be connected to ground. tstb 2 icmos test b: device test pin. must be connected to ground. symbol pin no. i/o/p type name/function
- 25 of 154 - txc-04201b-mb ed. 4, september 2001 ds1mx7 txc-04201b data sheet proprietary transwitch corporation information for use solely by its customers absolute maximum ratings and environmental limitations notes: 1. conditions exceeding the min or max values may cause permanent failure. exposure to conditions near the min or max values for extended periods may impair device reliability. 2. pre-assembly storage in non-drypack conditions is not recommended. please refer to the instructions on the "caution" label on the drypack bag in which devices are supplied. 3. test method for esd per mil-std-883d, method 3015.7. thermal characteristics power requirements parameter symbol min max unit conditions supply voltage v dd -0.3 +7.0 v note 1 dc input voltage v in -0.5 v dd + 0.5 v note 1 storage temperature range t s -55 150 o cnote 1 ambient operating temperature t a -40 85 o c 0 ft/min linear airflow moisture exposure level me 5 level per eia/jedec jesd22-a112-a relative humidity, during assembly rh 30 60 % note 2 relative humidity, in-circuit rh 0 100 % non-condensing esd classification esd absolute value 2000 v note 3 parameter min typ max unit test conditions thermal resistance from junction to ambient, ja 30 o c/w 0 ft/min linear airflow parameter min typ max unit test conditions v dd supply voltage 4.75 5.0 5.25 v i dd supply current 180 ma asynchronous mapping; configi = high. v dd = 5.0 v. t a = 25 o c p dd supply power 900 mw asynchronous mapping; configi = high. v dd = 5.0 v. t a = 25 o c i dd supply current 280 ma byte-synchronous map- ping; configi = low. v dd = 5.25v. t a = 85 o c. p dd supply power 1500 mw byte-synchronous map- ping; configi = low. v dd = 5.25v. t a = 85 o c.
- 26 of 154 - txc-04201b-mb ed. 4, september 2001 proprietary transwitch corporation information for use solely by its customers ds1mx7 txc-04201b data sheet input, output and input/output parameters input parameters for cmos input parameters for ttl input parameters for ttlp note: input has a 9k (nominal) internal pull-up resistor. output parameters for cmos or ttl 4 ma parameter min typ max unit test conditions v ih 0.7 x v dd v4.75 < v dd < 5.25 v il 0.3 x v dd v4.75 < v dd < 5.25 input leakage current 10 av dd = 5.25 input capacitance 2.5 pf parameter min typ max unit test conditions v ih 2.0 v 4.75 < v dd < 5.25 v il 0.8 v 4.75 < v dd < 5.25 input leakage current 10 a input capacitance 2.5 pf parameter min typ max unit test conditions v ih 2.0 v 4.75 < v dd < 5.25 v il 0.8 v 4.75 < v dd < 5.25 input leakage current 0.5 1.4 ma v dd = 5.25; input = 0 volts input capacitance 2.5 pf parameter min typ max unit test conditions v oh 2.4 v v dd = 4.75; i oh = -4.0 v ol 0.4 v v dd = 4.75; i ol = 4.0 i ol 4.0 ma i oh -4.0 ma t rise 11 ns c load = 50 pf t fa l l 7.0 ns c load = 50 pf leakage tristate 10 a 0 to 5.25 v input
- 27 of 154 - txc-04201b-mb ed. 4, september 2001 ds1mx7 txc-04201b data sheet proprietary transwitch corporation information for use solely by its customers output parameters for cmos open drain (4 ma) note: open drain requires use of 4.7k ohm external pull-up resistor. if this resistor is not provided the output behaves as tri state. output parameters for ttl 8 ma input/output parameters for cmos parameter min typ max unit test conditions v ol 0.5 v v dd = 4.75; i ol = 4.0 i ol 4.0 ma t fal l 7.0 ns c load = 50 pf high z leakage current 10 av dd = 5.25 parameter min typ max unit test conditions v oh 2.4 v v dd = 4.75; i oh = -8.0 v ol 0.4 v v dd = 4.75; i ol = 8.0 i ol 8.0 ma i oh -8.0 ma t rise 6.0 ns c load = 50 pf t fa l l 4.0 ns c load = 50 pf parameter min typ max unit test conditions v ih 0.7 x v dd v dd + 0.5 v 4.75 < v dd < 5.25 v il 0.3 x v dd v4.75 < v dd < 5.25 input leakage current 10 av dd = 5.25 input capacitance 2.5 pf v oh 2.4 v v dd = 4.75; i oh = -4.0 v ol 0.4 v v dd = 4.75; i ol = 4.0 i ol 4.0 ma i oh -4.0 ma t rise 6.0 ns c load = 50 pf t fa l l 4.0 ns c load = 50 pf
- 28 of 154 - txc-04201b-mb ed. 4, september 2001 proprietary transwitch corporation information for use solely by its customers ds1mx7 txc-04201b data sheet input/output parameters for ttl 8 ma parameter min typ max unit test conditions v ih 2.0 v 4.75 < v dd < 5.25 v il 0.8 v 4.75 < v dd < 5.25 input leakage current 10 av dd = 5.25 input capacitance 2.5 pf v oh 2.4 v v dd = 4.75; i oh = -8.0 v ol 0.4 v v dd = 4.75; i ol = 8.0 i ol 8.0 ma i oh -8.0 ma t rise 6.0 ns c load = 50 pf t fa l l 4.0 ns c load = 50 pf
- 29 of 154 - txc-04201b-mb ed. 4, september 2001 ds1mx7 txc-04201b data sheet proprietary transwitch corporation information for use solely by its customers timing characteristics detailed timing diagrams for the ds1mx7 are illustrated in figures 4 through 20, with values of the timing inter- vals tabulated below each diagram. all output times are measured with a maximum 25 pf load capacitance, unless otherwise indicated. timing parameters are measured at voltage levels of (v oh + v ol )/2 for output sig- nals or (v ih + v il )/2 for input signals. figure 4. tributary input timing notes: 1. for true byte-synchronous mode (control bits mode0 and mode1 = 01) lrclkn and rsyncn are outputs. for the other modes lrclkn and rsyncn are inputs. 2. lrclkn active edge may be inverted via control bit rcae (bit 6) in register 007h; as shown rcae = 0. rposn, rnegn, rsigln, rsyncn and rcvn are clocked in on the falling edge of lrclkn. for true byte-synchronous mode of operation, lrclkn and rsyncn are outputs. rsyncn is output delayed from the rising edge of lrclkn when control bit rcae = 0. parameter symbol min typ max unit lrclkn clock period t cyc 560 648 ns lrclkn high time t pwh 240 ns lrclkn low time t pwl 240 ns rpos/rneg/rsigl/rcv setup time to lrclk t su(1) 50 ns rpos/rneg/rsigl/rcv hold time after lrclk t h(1) 50 ns rsync pulse width as input t pw 500 750 ns rsync pulse width as output t pw 560 648 ns rsync setup as input before lrclk t su(2) 50 ns rsync hold as an input after lrclk t h(2) 50 ns rsync delay as output after lrclk t d 50 ns t cyc t pwh t pwl t su(1) t h(1) t d t pw lrclkn rposn rsyncn rcvn rsigln rnegn t su(2) t h(2) note: n=1-7 (see notes 1, 2) (see notes 1, 2)
- 30 of 154 - txc-04201b-mb ed. 4, september 2001 proprietary transwitch corporation information for use solely by its customers ds1mx7 txc-04201b data sheet figure 5. tributary output timing * ltclkn may be inverted via control bit tcae (bit 7) in register 007h; as shown tcae = 1. parameter symbol min typ max unit ltclkn clock period t cyc 637 648 656 ns ltclkn duty cycle, t pwh /t cyc -- 45 55 % tpos/tneg/tsigl output delay after lt c l k t od -5.0 50 ns tsync delay after ltclk t d -5.0 50 ns tsync pulse width t pw 637 648 656 ns t cyc t od t d t pw lt c l k n * tposn tsyncn tsigln tnegn note: n=1-7 t pwh
- 31 of 154 - txc-04201b-mb ed. 4, september 2001 ds1mx7 txc-04201b data sheet proprietary transwitch corporation information for use solely by its customers figure 6. signaling highway structure * tsync or rsync should be valid on the active edge of ltclk or lrclk, respectively. parameter symbol min typ max unit tsyncn/rsyncn clock period (n=1-7) t cyc 3.000 ms tsyncn/rsyncn pulse width (n=1-7) t pw one clock period of lt c l k o r lrclk* ns --- ds0 1 lsb s1/c1 msb f1/m1 ds0 lsb ds0 ds0 1 msb ds0 1 a1 lrclk lt c l k rsync tsync 24 ds0 24 ds0 1 ds0 1 ds0 1 24 ds0 1 ds0 1 ds0 1 ds0 1 ais ais a2 a3 a4 yel ais a5 a6 a8 yel a7 rpos/ tpos/ rsigl* tsigl* 4630 4631 0 1 2 3 4 5 192 193 194 195 196 197 198 multi-frame bit number multi-frame 24 * 1 * 2 note 1: * shown for 16-state signaling. see operation section. f1/m1 a1 ais ais a2 a3 a4 yel s1/c1 ais a5 a6 a8 yel a7 note 2: "---" in tpos, tneg, rpos, rneg, rsigl, and tsigl are unused bits (see operation section). note 3: ais is present in ds0 bit positions 16 through 192 (ds0 3 - ds0 24); bits 6 through 15 are unused. t cyc t pw --- --- --- --- --- -- rneg tneg note: n=1-7
- 32 of 154 - txc-04201b-mb ed. 4, september 2001 proprietary transwitch corporation information for use solely by its customers ds1mx7 txc-04201b data sheet figure 7. serial control port structure and timing parameter symbol min typ max unit lsclk clock period t cyc 560 648 ns lsclk high time t pwh 280 ns lsclk low time t pwl 280 ns lcsn delay time to lsclk t d(1) 100 324 350 ns lcsn inactive pulse width t pw 300 ns lsdi setup time to lsclk t su 100 ns lsdi hold time after lsclk t h(1) 100 ns lsclk to lcsn inactive t h(2) 100 ns lsdo delay after lsclk t d(2) 100 ns lsclk rise and fall times (10% - 90%) t r , t f 50 ns lcsn lsclk lsdi lsdo t pwh t cyc t pwl t su t h(1) t d(2) t h(2) t d(1) addrd0d1d2d3d4d5 d6 d7 t pw r/w addr addr addr addr addr addr data input/output address/command byte d0 d1 d2 d3 d4 d5 d6 d7
- 33 of 154 - txc-04201b-mb ed. 4, september 2001 ds1mx7 txc-04201b data sheet proprietary transwitch corporation information for use solely by its customers figure 8. telecom bus input timing - 6.48 mhz operation * for gapped clock applications, skipping a rising (and next falling) edge of dclk will extend the current low time to twice the listed value. all data is clocked in on the rising clock edge unless control bit tbrci (bit 4) in register 01eh is set to a 1, in which case all data is clocked in on the falling clock edge. parameter symbol min typ max unit dclk clock period t cyc 150 154.32 ns dclk high time t pwh 38 116 ns dclk low time t pwl 38 116* ns dd(0-7)/dpar setup time to dclk t su(1) 7.0 ns dd(0-7)/dpar hold time after dclk t h(1) 6.0 ns dspe setup time to dclk t su(2) 7.0 ns dspe hold time after dclk t h(2) 6.0 ns dc1j1v1 setup time to dclk t su(3) 7.0 ns dc1j1v1 hold time after dclk t h(3) 6.0 ns dc1j1v1 pulse width for c1 t pw 120 ns j1 v5 v4#1 c1 a1 t cyc t pwh t pwl t h(1) dpar dclk dc1j1v1 dspe dd(0-7) (input) (input) (input) (input) a2 v1#1 c1 j1, v1#1 t h(2) t su(3) t h(3) t su(1) t su(2) t pw
- 34 of 154 - txc-04201b-mb ed. 4, september 2001 proprietary transwitch corporation information for use solely by its customers ds1mx7 txc-04201b data sheet figure 9. telecom bus input timing - 19.44 mhz operation * for gapped clock applications, skipping a rising (and next falling) edge of dclk will extend the current low time to twice the listed value. all data is clocked in on the rising clock edge unless control bit tbrci (bit 4) in register 01eh is set to a 1, in which case all data is clocked in on the falling clock edge. parameter symbol min typ max unit dclk clock period t cyc 50 51.44 ns dclk high time t pwh 23 29 ns dclk low time t pwl 23 29* ns dd(0-7)/dpar setup time to dclk t su(1) 7.0 ns dd(0-7)/dpar hold time after dclk t h(1) 6.0 ns dspe setup time to dclk t su(2) 7.0 ns dspe hold time after dclk t h(2) 6.0 ns dc1j1v1 setup time to dclk t su(3) 7.0 ns dc1j1v1 hold time after dclk t h(3) 6.0 ns dc1j1v1 pulse width for an individual pulse (e.g., isolated j1) t pw 40 ns dc1j1v1 j1#1 to v1#1 delay (sts-3 mode) t d 3 cycles of dclk ns dc1j1v1 j1#1 to v1#1 delay (stm-1 mode) t d 6 cycles of dclk ns c1#1 j1#1 v1#1 j1#1 v1#1 v5 v4#1 c1#1 a1 t cyc t pwh t pwl t h(1) t su(1) t h(2) dpar t pw t su(3) t h(3) t su(2) dclk dc1j1v1 dspe dd(0-7) (input) (input) (input) (input) t d
- 35 of 154 - txc-04201b-mb ed. 4, september 2001 ds1mx7 txc-04201b data sheet proprietary transwitch corporation information for use solely by its customers figure 10. telecom bus output timing - 6.48 mhz operation * for gapped clock applications, skipping a rising (and next falling) edge of aclk will extend the current low time to twice the listed value. if control bit tbtci (bit 5) in register 01eh is set to a 0, all data is clocked in on the rising aclk clock edge and out on th e falling aclk clock edge, as is shown in the timing diagram. if control bit tbtci = 1, all data is clocked in on the falling clock edge and o ut on the rising clock edge of aclk. if control bit tbdd = 1, ad(0-7), apar and aadd are delayed one clock period from what is shown in the timing diagram with reference to aspe and ac1j1v1; input to daten must also be delayed one clock period of aclk. parameter symbol min typ max unit aclk clock period t cyc 150 154.32 ns aclk high time t pwh 38 116 ns aclk low time t pwl 38 116* ns ad(0-7)/apar delay time after aclk t d(1) 3.0 20 ns ad(0-7)/apar float time after aclk t f 3.0 20 ns aspe setup time to aclk t su(1) 7.0 ns aspe hold time after aclk t h(1) 3.0 ns ac1j1v1 setup time to aclk t su(2) 7.0 ns ac1j1v1 hold time after aclk t h(2) 3.0 ns ad(0-7)/apar delay time after daten t d(2) 15.9 ns ad(0-7)/apar delay time after daten t d(3) 13.6 ns aadd delay time after daten t d(4) 13.1 ns aadd delay time after daten t d(5) 13.2 ns aadd delay time after aclk t d(6) 0.0 16.8 ns ac1j1v1 pulse width for c1 t pw 120 ns ad(0-7)/apar rise/fall times (10% - 90%) t r , t f 10.9 ns j1 v1#1 v5 data c1 a1 t cyc t pwh t pwl apar daten t d(1) t d(2) t d(3) aadd t f t h(1) aclk ac1j1v1 aspe ad(0-7) (input) (output) (input) (input) (output) (input) a2 c1 j1, v1#1 t h(2) t su(1) t pw t d(4) t su(2) t d(6) t d(5)
- 36 of 154 - txc-04201b-mb ed. 4, september 2001 proprietary transwitch corporation information for use solely by its customers ds1mx7 txc-04201b data sheet figure 11. telecom bus output timing - 19.44 mhz operation * for gapped clock applications, skipping a rising (and next falling) edge of aclk will extend the current low time to twice the listed value. if control bit tbtci (bit 5) in register 01eh is set to a 0, all data is clocked in on the rising aclk clock edge and out on th e falling aclk clock edge, as is shown in the timing diagram. if control bit tbtci = 1, all data is clocked in on the falling clock edge and o ut on the rising clock edge of aclk. if control bit tbdd = 1, ad(0-7), apar and aadd are delayed one clock period from what is shown in the timing diagram with reference to aspe and ac1j1v1; input to daten must also be delayed one clock period of aclk. parameter symbol min typ max unit aclk clock period t cyc 50 51.44 ns aclk high time t pwh 23 29 ns aclk low time t pwl 23 29* ns ad(0-7)/apar delay time after aclk t d(1) 3.0 20 ns ad(0-7)/apar float time after aclk t f 3.0 20 ns aspe setup time to aclk t su(1) 7.0 ns aspe hold time after aclk t h(1) 3.0 ns ac1j1v1 setup time to aclk t su(2) 7.0 ns ac1j1v1 hold time after aclk t h(2) 3.0 ns ad(0-7)/apar delay time after daten t d(2) 15.9 ns ad(0-7)/apar delay time after daten t d(3) 13.6 ns aadd delay time after daten t d(4) 13.1 ns aadd delay time after daten t d(5) 13.2 ns aadd delay time after aclk t d(6) 0.0 16.8 ns ac1j1v1 pulse width for an individual pulse (e.g., isolated j1) t pw 40 ns ad(0-7)/apar rise/fall times (10% - 90%) t r , t f 10.9 ns ac1j1v1 j1#1 to v1#1 delay (sts-3 mode) t d(7) 3 cycles of dclk ns ac1j1v1 j1#1 to v1#1 delay (stm-1 mode) t d(7) 6 cycles of dclk ns c1#1 j1#1 v1#1 v5 data c1#1 a1 t cyc t pwh t pwl t h(2) t su(1) apar t pw t d(4) t su(2) daten t d(1) t d(6) t d(5) t d(2) t d(3) t f t h(1) aclk ac1j1v1 aspe ad(0-7) aadd (input) (output) (input) (input) (output) (input) j1#1 v1#1 t d(7)
- 37 of 154 - txc-04201b-mb ed. 4, september 2001 ds1mx7 txc-04201b data sheet proprietary transwitch corporation information for use solely by its customers figure 12. auxiliary port timing notes: * the first number is for 6.48 mhz operation; the second is for 19.44 mhz operation. 1. ** 25 pf load 2. auxiliary port transfers depend on the telecom bus add and drop assignments as controlled by registers x+04h and x+05h being valid, with control bit tbtval (bit 7) in register x+05h set to a 1 for auxiliary input timing (iapavo, iapado, and iapado) and contro l bit tbrval (bit 7) in register x+04h set to a 1 for auxiliary output timing (oapavo, oapado, oapdvo, and oapdto). also, for an inpu t byte to be fetched, the related control bits obapen, j2apen, z6apen and z7apen (bits 3-0) in register x+0bh must be set to a 1. parameter symbol min typ max unit oapcko or iapcko period (2 times dclk or aclk clock period) t cyc 308.64/ 102.88* ns delay - oapcko to oapavo, oapado, oapdvo or oapdto - iapcko to iapavo, iapado, iapdvo t d -2.0 5.0 ns fall time (90% - 10%) ?? ? o a pavo, o a pa d o, oapdvo, oapdto, iapavo, iapado, iapdvo t f 6.0 ns hold - iapdti after iapcko t h 3.0 ns oapcko or iapcko high time t pwh 40 50 60 % t cyc oapcko or iapcko low time t pwl 40 50 60 % t cyc rise time (10% - 90%) ?? -oapavo, oapado, oapdvo, oapdto, iapavo, iapado, iapdvo t r 6.0 ns setup - iapdti to iapcko t su 7.0 ns wait - oapavo or iapavo low time t w 1.0 t cyc t d d1 iapdti d2 d7 d8 d1 d6 d7 oapdto oapdvo iapdvo oapado iapado oapavo iapavo oapcko iapcko t pwl t cyc a0 a11 t pwh t w t d t su t h d8
- 38 of 154 - txc-04201b-mb ed. 4, september 2001 proprietary transwitch corporation information for use solely by its customers ds1mx7 txc-04201b data sheet figure 13. ring port timing *note: 25 pf load parameter symbol min typ max unit orpcko or irpcki period t cyc 514.4 ns delay - orpcko to orpfmo or orpdto t d 5.0 ns fall time (90% - 10%) ? ? oprcko, orpfmo or orpdto t f 6.0 ns hold - irpfmi or irpdti after irpcki t h 3.0 ns rise time (10% - 90%) ? - orpcko, orpfmo or orpdto t r 6.0 ns orpcko or irpcki high time t pwh 40 50 60 % t cyc orpcko or irpcki low time t pwl 40 50 60 % t cyc setup - irpfmi or irpdti to irpcki t su 7.0 ns t pwl t pwh t cyc t r t f t d t su t h ch1, rei-v ch1, rdi-vpd orpcko irpcki orpfmo irpfmi orpdto irpdti
- 39 of 154 - txc-04201b-mb ed. 4, september 2001 ds1mx7 txc-04201b data sheet proprietary transwitch corporation information for use solely by its customers figure 14. datacom mode output timing notes: 1. ltclkn can be inverted with the control bit tcae (bit 7) in register 007h. 2. ltclkn shown with tcae set to a 0. 3. 25 pf load parameter symbol min typ max unit ltclkn period t cyc 637 648 656 ns delay - ltclkn 1,2 to tgcon t d(1) 0.0 10 ns delay - ltclkn to tposn or tsyncn t d(2) -5.0 50 ns fall time (90% - 10%) 3 ? ltclkn, tgcon, tposn or tsyncn t f 6.0 ns ltclkn or tgcon high time t pwh 40% 50% 55% t cyc ltclkn or tgcon low time t pwl 40% 50% 55% t cyc rise time (10% - 90%) 3 - ltclkn, tgcon, tposn or tsyncn t r 6.0 ns t pwl t pwh t cyc t r t f t d(1) ds0 24, lsb f bit time lt c l k n tposn tsyncn ds0 1, msb tgcon (tneg) t d(2) note: n = 1 - 7
- 40 of 154 - txc-04201b-mb ed. 4, september 2001 proprietary transwitch corporation information for use solely by its customers ds1mx7 txc-04201b data sheet figure 15. datacom mode input timing notes: 1. lrclkn active edge may be inverted via control bit rcae (bit 6) in register 007h; as shown rcae = 1. rposn, rnegn, rsigln, rsyncn and rcvn are clocked in on the falling edge of lrclkn. for true byte-synchronous mode of operation (control bits mode0 and mode1 = 01), lrclkn and rsyncn are outputs. rsyncn is output delayed from the rising edge of lrclkn when control bit rcae = 0. 2. lrclkn shown with rcae set to a 1. 3. 25 pf load. parameter symbol min typ max unit lrclkn period t cyc 560 648 ns delay - lrclkn 1,2 to rgcon t d(1) 0.0 10 ns delay - lrclkn 1,2 to rsyncn if output t d(2) 50 ns fall time (90% - 10%) 3 ? rgcon, and lrclkn or rsyncn if outputs t f 6.0 ns hold - rposn or rsyncn if input after lrclkn 1,2 t h 50 ns lrclkn or rgco high time t pwh 240 ns lrclkn or rgco low time t pwl 240 ns rise time (10% - 90%) 3 - rgcon, and lrclkn or rsyncn if outputs t r 6.0 ns set-up - rposn or rsyncn if input to lrclkn 1,2 t su 50 ns t pwl t pwh t cyc t r t f t d(1) lrclkn rsyncn rgcon t d(2) note: n = 1 - 7 rposn rsyncn (output) (input) t su t h lsb f bit time msb ds0 24 ds0 1 (see note 1)
- 41 of 154 - txc-04201b-mb ed. 4, september 2001 ds1mx7 txc-04201b data sheet proprietary transwitch corporation information for use solely by its customers figure 16. intel microprocessor read cycle timing *note: pcki (not shown) is processor clock input, 8 to 20 mhz, which is required for device operation. parameter symbol min typ max unit addr(0-8) setup time to seli t su(1) 0.0 ns dtb(0-7) valid delay after rdyo t d(1) -1/2 cycle pcki* -10 ns dtb(0-7) float time after readi t f 1.0 3.0 5.0 ns seli setup time to readi t su(2) 0.0 ns readi pulse width t pw(1) 50 ns seli hold time after readi t h 0.0 ns rdyo delay after readi t d(2) 0.0 12 ns rdyo pulse width t pw(2) 2 cycles of pcki* 6 cycles of pcki* ns addr (0-8) dtb (0-7) seli readi rdyo t h t f t d(1) t pw(2) t d(2) t su(2) t su(1) t pw(1)
- 42 of 154 - txc-04201b-mb ed. 4, september 2001 proprietary transwitch corporation information for use solely by its customers ds1mx7 txc-04201b data sheet figure 17. motorola microprocessor read cycle timing *note: pcki (not shown) is processor clock input, 8 to 20 mhz, which is required for device operation. parameter symbol min typ max unit dtb(0-7) float time after seli t f(1) 1.0 10 ns addr(0-8) valid setup time to seli t su(1) 0.0 ns readi/wri setup time to seli t su(2) 0.0 ns seli pulse width t pw(1) 50 ns dtacko pulse width t pw(2) 2 cycles of pcki* 6 cycles of pcki* ns dtb(0-7) output delay after dtacko t d(1) -1/2 cycle pcki* -10 ns dtacko float time after seli t f(2) 1.0 10 ns dtacko delay after seli t d(2) 0.0 12 ns addr (0-8) dtb(0-7) seli readi/wri dtacko t f(2) t f(1) t d(1) t pw(2) t su(2) t su(1) t pw(1) t d(2)
- 43 of 154 - txc-04201b-mb ed. 4, september 2001 ds1mx7 txc-04201b data sheet proprietary transwitch corporation information for use solely by its customers figure 18. intel microprocessor write cycle timing *note: pcki (not shown) is processor clock input, 8 to 20 mhz, which is required for device operation. wait states only occur if a write cycle immediately follows a previous read or write cycle (e.g. ? read modify write ? or word-wide write). parameter symbol min typ max unit dtb(0-7) valid setup time to wri t su(1) 20 ns dtb(0-7) hold time after wri t h(1) 5.0 ns addr(0-8) setup time to seli t su(2) 0.0 ns seli setup time to wri t su(3) 0.0 ns wri pulse width t pw(1) 50 ns rdyo delay after wri t d 0.0 12 ns rdyo pulse width t pw(2) 0.0 6 cycles of pcki* ns addr (0-8) dtb(0-7) seli wri rdyo t h(1) t su(2) t pw(2) t d t su(3) t pw(1) t su(1)
- 44 of 154 - txc-04201b-mb ed. 4, september 2001 proprietary transwitch corporation information for use solely by its customers ds1mx7 txc-04201b data sheet figure 19. motorola microprocessor write cycle timing *note: pcki (not shown) is processor clock input, 8 to 20 mhz, which is required for device operation. wait states only occur if a write cycle immediately follows a previous read or write cycle (e.g. ? read modify write ? or word-wide write). parameter symbol min typ max unit dtb(0-7) valid setup time to seli t su(1) 20 ns dtb(0-7) valid hold time after seli t h(1) 5.0 ns addr(0-8) valid setup time to seli t su(2) 0.0 ns addr(0-8) valid hold time after seli t h(2) 3.0 ns readi/wri setup time to seli t su(3) 0.0 ns seli pulse width t pw(1) 50 ns dtacko pulse width t pw(2) 0.0 6 cycles of pcki* ns dtacko float time after seli t f 1.0 10 ns dtacko delay after seli t d 0.0 12 ns addr (0-8) dtb(0-7) seli readi/wri t f t pw(2) t su(2) t su(3) dtacko t su(1) t h(1) t pw(1) t d t h(2)
- 45 of 154 - txc-04201b-mb ed. 4, september 2001 ds1mx7 txc-04201b data sheet proprietary transwitch corporation information for use solely by its customers figure 20. boundary scan timing parameter symbol min max unit tck clock high time t pwh 50 ns tck clock low time t pwl 50 ns tms setup time to tck t su(1) 3.0 - ns tms hold time after tck t h(1) 2.0 - ns tdi setup time to tck t su(2) 3.0 - ns tdi hold time after tck t h(2) 2.0 - ns tdo delay from tck t d -7.0ns tms tdi tdo t d tck (input) (input) (input) (output) t h(2) t su(2) t su(1) t h(1) t pwh t pwl
- 46 of 154 - txc-04201b-mb ed. 4, september 2001 proprietary transwitch corporation information for use solely by its customers ds1mx7 txc-04201b data sheet operation general mapper application overview the ds1mx7 can be used in a wide variety of applications (see figures 48 through 49) that require either an asynchronous mapping of a ds1 signal into and out of a sonet or sdh payload in which the input clock and data are replicated at the output, or a byte-synchronous mapping of a ds1 signal into or out of a sonet or sdh payload in which not only is the input clock and data replicated at the output, but ds0 visibility and signal- ing information is replicated at the output. when used in an asynchronous application the ds1 side of the map- per connects to the line through ds1 line interface units (lius) that recover the 1.544 mhz from the data, provide clock and data to the ds1mx7, input clock and data from the ds1mx7 and format a line signal for transmission. a port is provided to control up to 7 lius from the ds1mx7. when used in byte-synchronous applications, ds1 framers may be inserted between the lius and the ds1mx7 to delineate the ds0s, extract and insert signaling, process ds0 and ds1 alarms, etc. the byte-synchronous applications may also be used for direct interface to sources of ds0s (e.g., time slot interchangers, pcm codecs) or to data sources like frac- tional t1 with hdlc protocol on n x ds0 channels. the ds1mx7 provides complete clock recovery of ds1 signals through a two stage digital filter, eliminating the need for special external de-jitter buffers. the ds1mx7 provides complete sonet or sdh low order path termination and origination functions (vt1.5/ tu-11) with alarm mapping to and from the ds1 line. on the system side, all that is required is a high order section, line and path termination origination function. the telecom bus provided in the ds1mx7 allows for multiple devices to be connected seamlessly to a transwitch sot-1e or sot-3 device, both of which supply these high order functions. a separate port is provided for access to optional overhead bytes. for redundant and ring applications a ring i/o port is provided as well as special alarm output and ds1 isolation input. a microproces- sor port is provided to configure the ds1mx7 as well as to provide interrupts for device wide/ telecom bus alarms as well as vt1.5/ tu-11 or ds1 alarms. one second shadow registers are provided to assist in the preparation of performance monitoring information. an ieee 1149.1 boundary scan function and an internal prbs generator/ analyzer are provided for manufacturing support. line interface selection each of the seven ds1mx7 channels can be individually programmed for asynchronous mode, byte-synchro- nous mode as clock master, or a modified byte-synchronous mode where the ds1mx7 channel is a clock slave in which pointer movements are generated as needed to map the incoming ds1 signal to the sonet/ sdh payload. the table below details the options present at the line interface. mode of operation line code rnegn tnegn mode1 mode0 lcode encod datacom x+00 bit 1 x+00 bit 0 x+00 bit 3 x+00 bit 2 x+00 bit 5 asynchronous ami data data 0 x 0 1 x asynchronous b8zs data data 0 x 1 1 x asynchronous nrz rcvn low 0 x 0 0 x asynchronous nrz rcvn high 0 x 1 0 x byte-synchronous lrclk/rsyncn out nrz rsigln input tsigln output 10xx 0 byte-synchronous (datacom) lrclk/rsyncn out nrz rgcon output tgcon output 10xx 1 modified byte-synchronous lrclk/rsyncn in nrz rsigln input tsigln output 11xx 0
- 47 of 154 - txc-04201b-mb ed. 4, september 2001 ds1mx7 txc-04201b data sheet proprietary transwitch corporation information for use solely by its customers asynchronous operation with the line interface each of the seven mappers in the ds1mx7 can be programmed to provide either a dual unipolar interface or a nrz interface. the dual unipolar interface is selected when a 1 is written into control bit encod (bit 2) in the control register located at address x+00h in the memory map. the x is (n x 040h), where n is the number of the mapper selected (1-7), as explained in the memory map section. the b8zs line or ami coder/decoder (codec) feature can be selected for the dual unipolar interface. the b8zs codec is selected by writing a 1 to control bit lcode (bit 3) in the register x+00h. a 0 will select an ami codec. the b8zs stands for bipolar with eight zero substitution, which is described in ansi document ansi t1.102-1993 and other bellcore doc- uments. the clock polarity of the input and output line clocks is selectable by writing the sense required to global control bits tcae and rcae (bits 7 and 6) in register 007h. when a mapper is configured for the dual unipolar mode, the line signal is monitored for loss of signal (los). los is detected if no transitions are present for 175 75 pulse positions. recovery occurs when a ones density of 12.5% or more is detected in 175 75 pulse posi- tions. a status bit loss (bit 5) in register x+10h indicates this condition. a mask, losm, a latched value, lose, a pm value, lospm and a fm value, losfm are available (bit 5) at register locations x+08h, x+14h, x+18h and x+1ch respectively. coding violations are counted in a 12-bit performance counter located at reg- ister locations x+22h and x+23h with shadow value in registers x+2ah and x+2bh. a counter overflow bit cvos (bit 0) in register x+10h is provided. a mask, cvom, a latched value, cvoe, a pm value, cvopm and a fm value, cvofm are available (bit 0) at register locations x+08h, x+14h, x+18h and x+1ch respectively. excessive zeros (8 or more for b8zs or 16 or more for ami) are included if control bit enzc (bit 4) in register x+00h is set to a 1. an ais indication is provided which checks to see if more than 99.9% ones occur in a 3 to 75 millisecond period or if less than 99.9% ones occur in a 3 to 75 millisecond period. status bit daiss (bit 3) in register x+10h indicates the ais condition. a mask, daism, a latched value, daise, a pm value, daispm and a fm value, daisfm are available (bit 3) at register locations x+08h, x+14h, x+18h and x+1ch respec- tively. the los condition can also be used to generate an ais (ds1 payload all-ones will be mapped in place of the received signal) if control bit los2ais (bit 6) in register x+01h is set to a 1. the coder block provides an ami/b8zs encoder. this block provides ais generation either from the micropro- cessor interface by control bit sdaisl (bit 3) in register x+03h when set to a 1 or optionally from various sys- tem conditions (vt ais/lop, signal label mismatch or unequipped) all of which are individually enabled by control bits vais2ais (bit 3 at x+01h), slm2ais (bit 2 at x+02h) and une2ais (bit 0 at x+02h) being set to a 1. a high level signal failure input on pin dfail will cause ds1 ais for all seven mappers. a 'transmit all-zeros' capability is provided to conserve power in an external line transceiver when ais is not required by setting control bit sdaisl (bit 3) in register x+03h to a 0 when control bit tbrval (bit 7) in register x+04h is also set to a 0 (drop slot not assigned). the connections between a ds1mx7 mapper and external line interface trans- ceivers are shown in figure 21 for dual unipolar mode. modified byte-synchronous (datacom) lrclk/rsyncn in nrz rgcon output tgcon output 11xx 1 mode of operation line code rnegn tnegn mode1 mode0 lcode encod datacom x+00 bit 1 x+00 bit 0 x+00 bit 3 x+00 bit 2 x+00 bit 5
- 48 of 154 - txc-04201b-mb ed. 4, september 2001 proprietary transwitch corporation information for use solely by its customers ds1mx7 txc-04201b data sheet figure 21. line interface for dual unipolar mode the nrz interface is selected when a 0 is written into control bit encod (bit 2) in register x+00h. the clock polarity of the line input and output clocks is selectable by writing to global control bits tcae and rcae (bits 7 and 6) in register 007h. options are provided for inverting the polarity of the transmit and receive data pins. a 1 written to control bit txnrzp (bit 0) in global register 007h inverts the polarity of the transmit data signal, tposn, while a 1 written to control bit rxnrzp (bit 4) in the same register inverts the polarity of the receive data signal rposn. in nrz mode, the rnegn pin may be used to input an external indication of coding viola- tions (rcvn). external coding violations are counted in the same 12-bit performance counter as described above. coding violations are counted when the input is high for rising edges of the line clock lrclkn. the same ais detector as described above for bipolar is available in nrz mode. los can be detected only exter- nally and input on pin laisn. by setting control bit explos (bit 6) in register x+00h to a 1, loss status plus latched event, mask, pm and fm functions are provided as described above. in the transmit direction, when the nrz mode is selected, the tnegn pin becomes a spare drive pin. when control bit encod (bit 2) in register x+00h is a 0, the output state of tnegn is defined by the value written to bit lcode (bit 3) in register x+00h (lcode set to a 0 is a low on tnegn and lcode set to a 1 is a high on tnegn). a typical interface between a mapper in the ds1mx7 and an external line transceiver is shown in figure 22 below for the nrz mode. tnegn, for example, may be used to select the encoding mode for the liu. figure 22. line interface for nrz mode line interface ds1mx7 receive rposn rnegn lrclkn tposn tnegn lt c l k n lcsn laisn lsclk lsdo lsdi cs los sclk sdi sdo rxtip rxring txtip txring transmit note: n is the channel number (1 - 7) other transceivers for channel n transceiver line interface tr a n s c e i v e r for channel n ds1mx7 receive rposn rcvn lrclkn tposn tnegn lt c l k n lcsn laisn lsclk lsdo lsdi cs los sclk sdi sdo rxtip rxring txtip txring transmit note: n is the channel number (1 - 7) other transceivers
- 49 of 154 - txc-04201b-mb ed. 4, september 2001 ds1mx7 txc-04201b data sheet proprietary transwitch corporation information for use solely by its customers byte-synchronous operation with the line interface for byte-synchronous operation the line interface operates in the nrz mode with rsigln and tsigln carrying the signaling information from/to an external framer using the negative polarity input and output pins. figure 23 is the basic byte-synchronous setup. typical applications are shown in figures 48 and 49. in byte- synchronous applications where signaling is not used, a datacom option is provided for connections to hdlc controllers or other devices that operate over the ds1 payload only. tgco and rgco are gapped clock outputs for clocking out or in data on tposn and rposn. the clock is gapped during the frame bit time every 125 ms. this option is available by setting control bit datacom (bit 5) in register x+00h to a 1. for byte-synchronous applications that require ds1-based performance monitoring (control bits mode1, 0 =10 in register x+00h bits 1 and 0 only), crc-6 is generated optionally for each superframe of data presented on rposn and inserted in the cn frame bit locations of the following superframe to be mapped. when control bit crc6 (bit 4) in register x+01h is set to a 1 crc-6 is both inserted and checked. after demapping crc-6 is checked. crc-6 errors share the 12-bit line code violation counter shadow register and overflow indications to support performance monitoring. crc-6 errors are counted in the 12-bit performance counter located at regis- ter locations x+22h and x+23h with shadow value in registers x+2ah and x+2bh. each esf superframe in which a calculated crc-6 value does not match the received crc-6 value increments the counter by one. a counter overflow bit cvos (bit 0) in register x+10h is provided. a mask, cvom, a latched value, cvoe, a pm value, cvopm and a fm value, cvofm are available (bit 0) at register locations x+08h, x+14h, x+18h and x+1ch respectively. . figure 23. byte-synchronous interface to a ds1 framer receive data and signaling highway operation the receive highway carries information from the framer to the ds1mx7. the highway is sub-divided into two time division multiplexed buses, one for the data (rposn), and one for signaling, frame bit and alarms (rsigln). these two buses are synchronous with the signals lrclkn and rsyncn, a 1.544 mhz clock and a 3 millisecond synchronization signal driven from the framer or the ds1mx7 depending on the mode of byte- synchronous operation. if the ds1mx7 operates in the modified byte-synchronous mode, receive clock and synchronization are inputs to the ds1mx7; if the ds1mx7 operates in true byte-synchronous mode, receive clock and synchronization are outputs of the ds1mx7. the data highway is a single-bit serial bus organized into 193-bit groups called frames. each frame consists of a spare bit position followed by twenty-four 8-bit data samples representing the 24 ds0s. 24 frames form a multiframe, the beginning of which is identified by a syn- chronization pulse, rsyncn. the rsyncn high pulse occurs one bit time before the first frame of the multi- frame and every 24 frames after that. the signaling highway, rsigln, is also divided into 193-bit frames. each frame consists of a frame bit followed by 192 bits of signaling and alarm information for the 24 data channels on the data highway. the frame bit pattern tracks the signaling bit pattern received from the system. the alarm ds1mx7 receive rposn rsigln/rgcon lrclkn tsigln/tgcon tposn lt c l k n rxtip rxring txtip txring transmit note: n is the channel number (1 - 7) ds1 framer and liu tsyncn rsyncn or other ds0 device
- 50 of 154 - txc-04201b-mb ed. 4, september 2001 proprietary transwitch corporation information for use solely by its customers ds1mx7 txc-04201b data sheet bits in the signaling highway follow the signaling bits. in each frame of 193 bits, four signaling bits are transmit- ted followed by a rai (yellow) alarm bit position. the bit positions coincident with ds0 3 through ds0 24 are all used for the ais alarm bit. signaling bits a1 through a4 occur in frame number one, followed by a5 through a8 in frame number two, and so on, ending with d21 through d24 in frame number 24, corresponding to the esf mode with 16-state signaling. for two-state or four-state signaling the b, c and d bits or the c and d bits are replaced by a bits or a and b bits respectively, as shown in the following table. the receive framing format and signaling format are shown in figures 24 and 25. the signaling information is stored in the rx signaling store block for mapping. the alarm information (ds1 ais and ds1 rai-yellow) is stored in the rx alarm control block and can be enabled to generate vt ais or rfi automatically. control bit sh2vais (bit 7) in register x+01h, when set to a 1, causes the ais alarm bits on the signaling highway to activate vt ais generation for the affected channel. when control bit yel2rfi (bit 1) in register x+01h is set to a 1, the rai-yellow alarm bit on the signaling highway causes the ds1mx7 mapper channel to send a vt rfi in the v5 byte. the status of these two signaling highway alarm bits is available as shdais and shyel (bits 7 and 6) in register x+20h as status only. when control bit ais2vais (bit 0) in register x+01h is set to a 1, the ds1mx7 will cause vt ais to be generated if the ds1 ais condition as defined above for the asynchronous mode of operation is detected. when control bit datacom (bit 5) in register x+00h is set to a 1, rsigln input becomes rgcon output, which is a gapped lrclkn clock with a gap of one lrclkn cycle wide occurring at the frame bit time of rposn every 125 microseconds. signaling bit positions on rsigln and tsigln frame sf/esf 16-st. rsigl; s 1 -s 4 tsigl; s 1 -s 4 4-state; s 1 -s 4 2-state; s 1 -s 4 1 f1/m1 a01, a02, a03, a04 a01, a02, a03, a04 a01, a02, a03, a04 a01, a02, a03, a04 2 s1/c1 a05, a06, a07, a08 a05, a06, a07, a08 a05, a06, a07, a08 a05, a06, a07, a08 3 f2/m2 a09, a10, a11, a12 a09, a10, a11, a12 a09, a10, a11, a12 a09, a10, a11, a12 4 s2/f1 a13, a14, a15, a16 a13, a14, a15, a16 a13, a14, a15, a16 a13, a14, a15, a16 5 f3/m3 a17, a18, a19, a20 a17, a18, a19, a20 a17, a18, a19, a20 a17, a18, a19, a20 6 s3/c2 a21, a22, a23, a24 a21, a22, a23, a24 a21, a22, a23, a24 a21, a22, a23, a24 7 f4/m4 b01, b02, b03, b04 b01, b02, b03, b04 b01, b02, b03, b04 a01, a02, a03, a04 8 s4/f2 b05, b06, b07, b08 b05, b06, b07, b08 b05, b06, b07, b08 a05, a06, a07, a08 9 f5/m5 b09, b10, b11, b12 b09, b10, b11, b12 b09, b10, b11, b12 a09, a10, a11, a12 10 s5/c3 b13, b14, b15, b16 b13, b14, b15, b16 b13, b14, b15, b16 a13, a14, a15, a16 11 f6/m6 b17, b18, b19, b20 b17, b18, b19, b20 b17, b18, b19, b20 a17, a18, a19, a20 12 s6/f3 b21, b22, b23, b24 b21, b22, b23, b24 b21, b22, b23, b24 a21, a22, a23, a24 13 f1/m7 c01, c02, c03, c04 c01, c02, c03, c04 a01, a02, a03, a04 a01, a02, a03, a04 14 s1/c4 c05, c06, c07, c08 c05, c06, c07, c08 a05, a06, a07, a08 a05, a06, a07, a08 15 f2/m8 c09, c10, c11, c12 c09, c10, c11, c12 a09, a10, a11, a12 a09, a10, a11, a12 16 s2/f4 c13, c14, c15, c16 c13, c14, c15, c16 a13, a14, a15, a16 a13, a14, a15, a16 17 f3/m9 c17, c18, c19, c20 c17, c18, c19, c20 a17, a18, a19, a20 a17, a18, a19, a20 18 s3/c5 c21, c22, c23, c24 c21, c22, c23, c24 a21, a22, a23, a24 a21, a22, a23, a24 19 f4/m10 d01, d02, d03, d04 d01, d02, d03, d04 b01, b02, b03, b04 a01, a02, a03, a04 20 s4/f5 d05, d06, d07, d08 d05, d06, d07, d08 b05, b06, b07, b08 a05, a06, a07, a08 21 f5/m11 d09, d10, d11, d12 d09, d10, d11, d12 b09, b10, b11, b12 a09, a10, a11, a12 22 s5/c6 d13, d14, d15, d16 d13, d14, d15, d16 b13, b14, b15, b16 a13, a14, a15, a16 23 f6/m12 d17, d18, d19, d20 d17, d18, d19, d20 b17, b18, b19, b20 a17, a18, a19, a20 24 s6/f6 d21, d22, d23, d24 d21, d22, d23, d24 b21, b22, b23, b24 a21, a22, a23, a24
- 51 of 154 - txc-04201b-mb ed. 4, september 2001 ds1mx7 txc-04201b data sheet proprietary transwitch corporation information for use solely by its customers figure 24. system interface receive framing format figure 25. system interface receive signaling format rsyncn lrclkn f = frame bit; frame 1 frame 2 frame 3 frame 24 one frame (193 bits) channel 1 channel 2 channel 3 channel 24 rposn 8 bits per channel f s 1 s 2 s 3 s 4 y-- - -------- aaaaaaaa aaaaaaaa aaaaaaaa a = ais; y = rai-yellow alarm; s1, s2, s3, s4 = signaling bits; - = not assigned 3 ms rsigln ? rsyncn lrclkn frame 1 frame 2 frame 23 frame 24 first 5 bits rsigln 3 ms of frame first 5 bits of frame first 5 bits of frame first 5 bits of frame first 5 bits of frame f a 0 1 a 0 4 a 0 2 a 0 3 f a 0 5 a 0 8 a 0 6 a 0 7 f c 0 5 c 0 8 c 0 6 c 0 7 f d 1 7 d 2 0 d 1 8 d 1 9 f d 2 1 d 2 4 d 2 2 d 2 3 rposn
- 52 of 154 - txc-04201b-mb ed. 4, september 2001 proprietary transwitch corporation information for use solely by its customers ds1mx7 txc-04201b data sheet transmit data and signaling highway operation the transmit highway carries information from the ds1mx7 to the framer. the highway is sub-divided into two time division multiplexed buses, one for the data (tposn) and one for signaling, frame bits and alarms (tsigln). these two buses are synchronous with the signal ltclkn, a 1.544 mhz clock that is driven from the ds1mx7. the data highway is a single bit-serial bus that is organized into 193-bit groups called frames. each frame consists of a frame bit followed by twenty-four 8-bit data samples. each of the 8-bit data samples repre- sents a single ds0 on the receive highway. the 193-bit frames are grouped into a 24-frame multiframe. in order to help locate the beginning of a frame and extract signaling information, the ds1mx7 sources a syn- chronization signal, tsyncn. in byte synchronous mode only; tsyncn is present if a standard compliant p 1 p 0 pattern is present in the vt1.5 or tu-11 as shown in figure 2. the tsyncn high pulse occurs one bit time before the first frame in the multiframe and every 24 frames after that. the signaling highway, tsigln, is also divided into 193-bit frames and is organized in an identical fashion to rsigln (see the table above for sig- naling bit assignments). the alarm bits in the signaling highway follow the signaling bits. in each frame of 193 bits, four signaling bits are transmitted followed by a rai (yellow) alarm bit position. the bit positions coincident with ds0 3 through ds0 24 are all used for the ais alarm bit. signaling bits a1 through a4 occur in frame num- ber one followed by a5 through a8 in frame number two ending with d21 through d24 in frame number 24, cor- responding to the esf mode with 16-state signaling. for two-state or four-state signaling the b, c and d bits or the c and d bits are replaced by a bits or a and b bits respectively, as shown in the table above. ais or yellow alarm sourced by the ds1mx7 are output in the same positions as on rsigln. these alarm bits may be used to force ds1 yellow or ds1 ais automatically in the qt1f- plus . control bit vais2ais (bit 3) in register x+01h, when set to a 1, causes the detection of vt-lop or vt ais to set the ais bits on tsigln unless control bit datacom (bit 5) in register x+00h is set to a 1. similarly, if control bits slm2ais (bit 2) and une2ais (bit 0) in register x+02h are set to a 1, and if either a signal label mismatch or unequipped condition exists, the ais bits on the signaling highway are set to a 1 unless control bit datacom is set to a 1. setting control bit sdaisl (bit 3) in register x+03h to a 1 will also set the ais bits in tsigln unless control bit datacom is set to a 1. control bit sdaisl set to a 1 or control bits vais2ais, slm2ais or une2ais set to a 1 and the condition vt lop/ais, signal label mismatch or unequipped occurs will cause an all-ones signal to be generated on tposn without regard for control bits datacom or mode1. likewise, the yellow alarm bit on the signaling highway may be set if control bit rfi2yel (bit 2) in register x+01h and an rfi alarm is detected, or if control bit syell (bit 2) in register x+03h is set to a 1 when control bit mode1 (bit 1) in register x+00h is set to a 1 indicating byte-synchronous operation and datacom (bit 5) in the same register is set to a 0 indicating tsigln is not used for gapped clock output. the frame bits received from the vt1.5/ tu-11 are available on tsigln as well; they track the signaling bits and may be used for fdl extraction. when control bit datacom (bit 5) in register x+00h is set to a 1, tsigln output becomes tgcon output, which is a gapped ltclkn clock with a gap one ltclkn cycle wide occurring at the frame bit time of tposn every 125 microseconds. system interface transmit framing format and signaling format are shown in figures 26 and 27.
- 53 of 154 - txc-04201b-mb ed. 4, september 2001 ds1mx7 txc-04201b data sheet proprietary transwitch corporation information for use solely by its customers figure 26. system interface transmit framing format figure 27. system interface transmit signaling format the tx signaling store and the tx alarm control blocks buffer the signaling and alarm information to be sent on the signaling highway. the signaling bits are output as shown in the table above as well as in figure 27. to support certain protection schemes, pin cso when tied low will cause the transmit line interface leads (ltclkn, tnegn/tsigln/tgcon, tposn, and tsyncn) to be driven to a logic low. f = frame bit; frame 1 frame 2 frame 3 frame 24 one frame (193 bits) channel 1 channel 2 channel 3 channel 24 8 bits per channel f s 1 s 2 s 3 s 4 y-- - -------- aaaaaaaa aaaaaaaa aaaaaaaa a = ais; y = yellow alarm; s1, s2, s3, s4 = signaling bits; - = not assigned 3 ms tsyncn ltclkn tposn tsigln f tsyncn ltclkn frame 1 frame 2 frame 23 frame 24 first 5 bits tsigln 3 ms of frame first 5 bits of frame first 5 bits of frame first 5 bits of frame first 5 bits of frame f a 0 1 a 0 4 a 0 2 a 0 3 f a 0 5 a 0 8 a 0 6 a 0 7 f c 0 5 c 0 8 c 0 6 c 0 7 f d 1 7 d 2 0 d 1 8 d 1 9 f d 2 1 d 2 4 d 2 2 d 2 3 tposn
- 54 of 154 - txc-04201b-mb ed. 4, september 2001 proprietary transwitch corporation information for use solely by its customers ds1mx7 txc-04201b data sheet the synchronizer, mapper and overhead generator the synchronizer/mapper block operates in three different modes, programmable on a per channel basis as described above in the line interface section. the synchronizer/mapper is the heart of the mapping side of the device. it synchronizes the 1.544 mb/s data stream to the sonet/sdh clock domain, it maps the data stream to the virtual tributary (vt1.5/ tu-11) and it inserts the low order path overhead for performance moni- toring and administrative purposes. figure 2 shows the result of the synchronization, mapping and overhead insertion functions to form a vt1.5/ tu-11 for asynchronous or byte-synchronous mode. the synchronization function adjusts approximately 772 ds1 bits so that they fit into a vt1.5 / tu-11 which is 500 microseconds long. the ds1 signal, whether framed to sf or esf formats or framed to another format, generates 193 bits every 125 microseconds. as shown in figure 2, three opportunities are provided for 193 bits (i plus 24 bytes) and one opportunity for 192 (no st bits used for information), 193 (one st bit used for infor- mation) or 194 bits (both st bits used for information) in the vt1.5/ tu-11 for the asynchronous mode. two stuffing control bits (c 1 and c 2 ) repeated twice are provided in every vt1.5/ tu-11 to indicate if a stuffing bit opportunity is to be used for information or stuff; for c 1 c 1 c 1 = 000 indicates that s t1 is used for an information bit and c 1 c 1 c 1 = 111 indicates that s t1 is used for a stuff bit. c 2 is treated likewise. this mechanism allows majority voting to be used at the desynchronizer, providing a robust solution at high bit error rates. the ds1mx7 has an input buffer that is written by the ds1 line clock and read by the sonet/ sdh clock. the stuffing control in the ds1mx7 uses the depth of this input buffer to set the value of c 1 and c 2 . buffer overflow/ underflow is a fault condition of the input caused by the input frequency being outside the stuffing range for asynchronous mapping (approximately + 230 hz). this condition will be passed to the microprocessor inter- face as an alarm (map error). status bit mps (bit 4) in register x+10h indicates the map error status; mask mpm, latched event mpe, performance value mppm and hard fault value mpfm are all bit 4 of registers x+08h, x+14h, x+18h and x+1ch respectively. the stuffing mechanism in the ds1mx7 employs threshold modulation such that a desynchronizer will meet gr-253-core category i jitter requirements. this is done by using srclk to vary the input ds1 clock ? s phase for every sequential vt1.5/ tu-11 such that the stuffing pat- tern varies at a frequency high enough to be filtered easily by the desynchronizer. this prevents a ds1 clock that is a few hz different from a sonet/sdh derived 1.544 mhz reference clock from generating jitter spikes when desynchronized. this feature can be turned off for testing purposes by setting global control bit tmdis (bit 2) in register 03dh to a 1. byte-synchronous mapping permits full ds0 and signaling visibility as is shown in figure 2. the 24 bytes every 125 microseconds are now 24 ds0s; the stuffing mechanism is replaced by a p 1 /p 0 pattern that is used to identify different sf and esf frame bits as well as which signaling bits are being sent and which go to what ds0s. byte-synchronous mapping performs synchronization in two different ways. when lrclkn and rsyncn are outputs they are derived from signal lo, which must be sourced from the sonet/sdh payload timing (aclk, aspe and ac1j1v1). as such, exactly 24 ds0s, one frame bit and four signaling bits are mapped every 125 microseconds. rsyncn output defines the start of the first of six vt superframes (the p 1 / p 0 pattern goes from 11 to 00) that form a 3.0 ms multiframe. if the source of the ds1 has a different clock than at pin lo, an external slip buffer must be provided; the transwitch qt1f- plus (txc-03103) provides this func- tion. since some applications do not want to have the added delay of up to two ds1 frames for slip buffering (e.g. tr-496 objective 3-6), a modified version of byte-synchronous mapping is provided where lrclkn and rsyncn are inputs for floating vt1.5/ tu-11 mode. on the tributary or ds1 line side it operates from the input timing block, where data is fed into the block. on the system side it operates off of telecom bus sonet/sdh drop timing. ds1 line side clock and multi-frame synchronization uses the buffering supplied by this block. if the input buffer becomes too full the synchronizer requests a pointer decrement to be generated by the vt ter- mination block which aligns the virtual container to the virtual tributary; this will cause an extra byte of data to be read out of the input buffer in a 500 microsecond period. in figure 2 the v3 byte will be skipped and every- thing will shift up one byte. likewise, if the input buffer is too empty the synchronizer requests a pointer incre- ment causing the v3 position to be repeated and one less byte of data will be read out of the input buffer in a 500 microsecond period. buffer overflow/underflow is a fault condition of the input caused by the loss of frame
- 55 of 154 - txc-04201b-mb ed. 4, september 2001 ds1mx7 txc-04201b data sheet proprietary transwitch corporation information for use solely by its customers synchronization (if control bit lof2vais (bit 5) in register x+01h is set to a 1) for this mode. this condition will be passed to the microprocessor interface as an alarm (map error). status bit mps (bit 4) in register x+10h indicates the map error status; mask mpm, latched event mpe, performance value mppm and hard fault value mpfm are all bit 4 of registers x+08h, x+14h, x+18h and x+1ch respectively. rsyncn input defines the start of the first of six vt superframes (the p 1 /p 0 pattern goes from 11 to 00), as shown in the table below. the mapper takes the output of the synchronizer and adds the overhead bits and bytes to it. the o, j2, z6 and z7 positions are driven with the values stored in registers x+36h (o-bits), x+37h (j2 byte), x+38h (z6/n2 byte) and x+39h (z7/k4 byte) unless the auxiliary port is used. if the auxiliary port is used and the enable bit (obapen, j2apen, z6apen or z7apen, bits 3 - 0 in register x+0bh) for the specific byte is set to a 1, the byte is brought in from the auxiliary port and inserted into the overhead byte position as well as in the above register locations. for asynchronous operation only, the eight o-bits and six c 1 and c 2 bits are included as shown in figure 2. for byte-synchronous operation the mapper also multiplexes into the payload the data from the rx signaling store, which contains both the abcd signaling bits for each ds0 and also the ds1 sf or esf frame bits. since the signaling and framing bits in a framed ds1 take 3.0 milliseconds for a single esf superframe, six 500-microsecond vt superframes are required to define it. the p 1 /p 0 bits for the byte-syn- chronous mapping are coded to identify the signaling and framing bits as shown in the table below. refer to figure 2 for the signaling and p 1 /p 0 bit positions. the signaling bits are shown for esf; for sf or esf with four- state signaling the cndn bits are the anbn bits repeated; for two-state signaling anbncndn becomes anananan in the table below. whether the frame bits are provided or not, the ds1mx7 can be set to calculate crc-6 over the ds0s only, inserting them in the crc positions in the table below if control bit crc6 (bit 4) in register x+01h is set to a 1. the transwitch qt1f- plus (txc-03103) supports the insertion of specific abcd signaling codes for ds0 ais and ds0 rai via its signaling buffer write capability and it optionally forces the robbed bit positions to all 1 to support byte-synchronous gr-253-core signaling conditional requirements.
- 56 of 154 - txc-04201b-mb ed. 4, september 2001 proprietary transwitch corporation information for use solely by its customers ds1mx7 txc-04201b data sheet . signaling and frame bit assignments for byte-synchronous modes p 1 p 0 s 1 s 2 s 3 s 4 f for sf f for esf time (ms) 0 0 a1 a2 a3 a4 f t1 m 1 0.125 0 0 a5 a6 a7 a8 f s1 crc 1 0.250 0 0 a9 a10 a11 a12 f t2 m 2 0.375 0 0 a13 a14 a15 a16 f s2 fps 1 0.500 0 0 a17 a18 a19 a20 f t3 m 3 0 0 a21 a22 a23 a24 f s3 crc 2 0 1 b1 b2 b3 b4 f t4 m 4 0 1 b5 b6 b7 b8 f s4 fps 2 1.000 0 1 b9 b10 b11 b12 f t5 m 5 0 1 b13 b14 b15 b16 f s5 crc 3 0 1 b17 b18 b19 b20 f t6 m 6 0 1 b21 b22 b23 b24 f s6 fps 3 1.500 1 0 c1 c2 c3 c4 f t1 m 7 1 0 c5 c6 c7 c8 f s1 crc 4 1 0 c9 c10 c11 c12 f t2 m 8 1 0 c13 c14 c15 c16 f s2 fps 4 2.000 1 0 c17 c18 c19 c20 f t3 m 9 1 0 c21 c22 c23 c24 f s3 crc 5 1 1 d1 d2 d3 d4 f t4 m 10 1 1 d5 d6 d7 d8 f s4 fps 5 2.500 1 1 d9 d10 d11 d12 f t5 m 11 1 1 d13 d14 d15 d16 f s5 crc 6 1 1 d17 d18 d19 d20 f t6 m 12 1 1 d21 d22 d23 d24 f s6 fps 5 3.000 legend: an, bn, cn, and dn are the signaling bits for 16-state signaling in esf format and represent the bits robbed from ds0 ? n ? in frames 6, 12, 18 and 24. for 4-state signaling cn and dn are interpreted as an and bn. for 2-state signaling bn, cn and dn are interpreted as an. f tn are the frame alignment bits for sf; f sn are the signaling framing bits for sf. fps n are the esf frame alignment bits; crc n are the crc-6 bits in esf; m n are the facility data link bits in esf.
- 57 of 154 - txc-04201b-mb ed. 4, september 2001 ds1mx7 txc-04201b data sheet proprietary transwitch corporation information for use solely by its customers pointer generation and telecom bus slot selection in the ds1mx7 device only the vt1.5/tu-11 termination is provided. the vt termination block accepts data, alarms and timing information from the synchronizer/mapper block and completes the generation of the vt1.5/ tu-11 started in the synchronizer/mapper block. each mapper can add its vt1.5/ tu-11 to any one of 28 or 84 slots as shown in figure 39 and figure 40 below. control bit tbtval (bit 7) in register x+05h must be set to a 1 for the vt1.5/ tu-11 to be added to the telecom bus. bits 6-5 of the same register determine the sts-1, au3 or tug-3 number (one of three). bits 4- 2 in this same register determine the vt group or tug-2 number (one of seven) and bits 1 and 0 determine the vt1.5 or tu-11 number (one of four). for asynchronous operation a fixed position for v5 is generated (offset of 78 with a valid v1 and v2; next vt/tu byte after v1) as shown in figure 2 above. for the modified version of byte-synchronous operation, the vt synchronous payload envelope or virtual container (vt-spe/ vc) moves to accommodate frequency differ- ences as described above. the vt termination block provides a pointer generation state machine that follows the bellcore, ansi and itu rules in t1.105, gr-253-core and g.709 by generating no more than a single movement every four vt superframes (2.0 ms). loss of frame or signal will cause a new start of vt superframe position when the signal recovers; this will force a new data flag (ndf) request of the vt termination block. on exiting ais the synchronizer block will re-center its buffer and request an ndf. the synchronizer block will also look for a change in the expected position of rsyncn and indicate an ndf request upstream. valid v1 and v2 bytes are always generated. v3 is used as a stuff opportunity when pointer decrements are done and v4 is unused. for true byte-synchronous operation a fixed position for v5 results from the fact that clock and frame synchronization are outputs which are synchronous with the sonet/sdh structure even though the pointer generation state machine is enabled. two four-bit counters (one to count increments generated and one to count decrements generated) are provided to track frequency deviations. these counters are located at x+25h (bits 7-4 for increment and bits 3-0 for decrement) with latched shadow values located in the same bits at x+2dh. if an overflow of either counter occurs, status bit pgos (bit 1) in register x+10h is set to a 1 and an interrupt can be generated; one second polling/clearing of this counter is recommended. a mask pgom, latched event pgoe, performance value pgopm and hard fault value pgofm are all bit 1 of registers x+08h, x+14h, x+18h and x+1ch respectively. the v5 byte is generated for all modes. v5 is formed from a bit-interleaved parity calculation, a signal label stored in register x+07h bits 2-0, and three alarm bits, rei-v, rfi-v and rdi-v. now that the entire virtual con- tainer is formed, the bip-2 bits are calculated and inserted in the v5 byte as shown in figure 2 based on the previous vt-spe/ vc; the msb is chosen to make the sum of the odd bits of every byte in the vt-spe even parity and the second bit is chosen to make the sum of all the even bits of every byte in the vt-spe even. the alarm bits are mapped based on the results of demapping, ds1 line conditions or via the ring port as shown in the table below. when the ring port is enabled, v5 only gets rei-v and rdi-v from this port. rfi-v is used in byte-synchronous modes only and comes from a microprocessor-forced value as the result of software- based failure detection (usually in the 2 to 3 second range) of a persisting line, section or high or low order path defect or via the signaling highway as the result of a ds1 rai or yellow alarm.
- 58 of 154 - txc-04201b-mb ed. 4, september 2001 proprietary transwitch corporation information for use solely by its customers ds1mx7 txc-04201b data sheet : to support three-bit rdi, the z7 byte is also encoded based on different demap conditions or on the three-bit rdi values supplied by the ring port. the unused bits in z7/k4 are supplied from the auxiliary port or the internal register at x+39h; figure 2 shows the z7 byte usage for three-bit rdi. the table below defines the conditions that generate three-bit rdi. when the alarms occur in the demap side of the ds1mx7 and are sup- plied internally or via the ring port, the higher priority code always replaces the lower priority code. v5 generation alarm sources and controls alarm microproc. force demap conditions ds1 line conditions enable controls ring bit ring enable bip-2 sbipe = 1, reg. x+03h, bit 5. ectl(7-0) in reg. 01dh sets number of times none none febeis = 1, reg. x+02h, bit 1, enables microproc. forcing. febeis = 0 for nor- mal calculation. none none rei-v = 1 sfebe = 1, reg. x+03h, bit 5. ectl(7-0) in reg. 01dh sets number of times one or two bip-2 errors none febeis = 1, reg. x+02h, bit 1, enables microproc. forcing. febeis = 0 for nor- mal calculation. rei-v = 1 ringen = 1, reg. x+0bh, bit 4 rfi-v = 1 srfi = 1, reg. x+03h, bit 1. software integrated failure state from los, lof, ais-l/p/ v, lop-p/v, uneq- p/v, & plm-p/v yellow via signaling highway; y-bit = 1 yel2rfi = 1, reg. x+01h, bit 1. none none rdi-v = 1 srdi-vsd = 1, reg. x+02h, bit 6. ais-v, lop-v none rdiis = 1 reg. x+02h, bit 3 enables microproc. forcing. rdiis = 0 for normal insertion from demap rdi-vsd = 1 ringen = 1 reg. x+0bh, bit 4 srdi-vcd = 1, reg. x+02h, bit 5. uneq-v rdi-vcd = 1 z7 three-bit rdi generation sources and controls alarm microproc. force demap conditions z7 code bits 5, 6, 7 priority enable controls ring bit ring enable rdi-vsd = 1 srdi-vsd = 1, reg. x+02h, bit 6. ais-v, lop-v 101 1 rdiis = 1, reg. x+02h, bit 3 enables microproc. forcing. rdiis = 0 for normal insertion from demap rdi-vsd = 1 ringen = 1, reg. x+0bh, bit 4 rdi-vcd = 1 srdi-vcd = 1, reg. x+02h, bit 5. uneq-v 110 2 rdi-vcd = 1 rdi-vpd = 1 srdi-vpd = 1, reg. x+02h, bit 7. plm-v 010 3 rdi-vpd = 1 none none no defects 001 4 all 0
- 59 of 154 - txc-04201b-mb ed. 4, september 2001 ds1mx7 txc-04201b data sheet proprietary transwitch corporation information for use solely by its customers vt/tu idle and ais insertion are performed at this point. microprocessor interface controls for v5 allow either a valid v5 with an all-zeros payload to be generated for idle or an all-zeros v5 for unequipped. control bit idle (bit 7) in register x+00h, when set to a 0, powers down the channel. control bits rdiis, febeis, sbipe, sfebe, transmit signal label, srdi-vpd, srdi-vsd, srdi-vcd and tx z7 all have an effect on the idle sig- nal sent. the table below provides recommended settings for idle and unassigned (but still monitored) and idle but unequipped (not monitored). note: x = don ? t care control bits sh2vais, los2ais, lof2vais, ais2vais, sdaiss and svtais, together with the mapping mode control bits (mode1, mode0 and datacom) and the line decoder controls (encod and explos) deter- mine whether ais or vt ais is mapped. the ais alarm bits on the signaling highway, loss of frame in modi- fied byte-synchronous mode, microprocessor command, an all-ones detected in the decoder, a los condition detected in the decoder and the los condition via a signal on the lais pin can be used to generate an ais (ds1 payload all-ones will be mapped in place of the received signal) or vt ais (payload, overhead and v1 plus v2 bytes all-ones). the table below details the feature. idle control of ds1mx7 control bit valid v5 & z7 payload = 0 payload z7 & v5 = 0 idle; reg. x+00h, bit 7 0 0 rdiis; reg. x+02h, bit 3 0 1 srdi-vpd; reg. x+02h, bit 7 x 0 srdi-vsd; reg. x+02h, bit 6 x 0 srdi-vcd; reg. x+02h, bit 5 x 0 febeis; reg. x+02h, bit 1 0 1 sfebe; reg. x+03h, bit 7 0 0 sbipe; reg. x+03h, bit 5 0 0 tx z7; reg. x+39h, bits 7-0 00h 00h ringen (if ring port used); reg. x+0bh, bit 4 1 0
- 60 of 154 - txc-04201b-mb ed. 4, september 2001 proprietary transwitch corporation information for use solely by its customers ds1mx7 txc-04201b data sheet . note: x = don ? t care vt/tu pointer tracking and telecom bus slot selection in the ds1mx7 device only the vt1.5/tu-11 termination is provided. the vt termination block accepts data, high order alarms and timing information from the telecom bus interface block, tracks the vt1.5/ tui-11 pointer and extracts the alarms. the vt termination block also provides data, alarms and control to the desyn- chronizer/demapper block. all operations (pointer interpretation, pointer generation, vt/tu lop detection, vt/ tu ais detection, etc.) are performed in accordance with gr-253-core, g.709, and g.783. each mapper can drop its vt1.5/ tu-11 from any one of 28 or 84 slots as shown in figure 39 and figure 40 below. control bit tbrval (bit 7) in register x+04h must be set to a 1 for the vt1.5/ tu-11 to be dropped from the telecom bus. bits 6-5 of the same register determine the sts-1, au3 or tug-3 number (one of three). bits 4-2 in this same register determine the vt group or tug-2 number (one of seven) and bits 1 and 0 determine the vt1.5 or tu-11 number (one of four). the values chosen may be the same or different from the add bus values. the starting location of the v1 byte is determined by the v1 pulses in the dc1j1v1 signals. the vt/tu pointer bit assignment for the v1 and v2 bytes is shown below. the alignment is necessary to determine the starting locations of the v5 byte and the other bytes that are carrying the 1544 kbit/s format. ais and vt-ais generation sources and controls alarm generated microproc. force ds1line conditions mode1 reg. x+00h, bit 1 mode0 reg. x+00h, bit 0 datacom reg. x+00h, bit 5 enable controls ds1 ais sdaiss = 1, reg. x+03h, bit 6 all-ones x x x none (passes through) any x x x none lais pin high 0 x x explos =1, reg. x+00h, bit 6 & los2ais = 1, reg. x+01h, bit 6 los detected 0 x x encod = 1, reg. x+00h, bit 2 & los2ais = 1, reg. x+01h, bit 6 vt ais svtais = 1, reg. x+03h, bit 0 any x x x none lais pin high 1 x x explos =1, reg. x+00h, bit 6 & los2ais = 1, reg. x+01h, bit 6 tsigln a-bits = 1 1 x 0 sh2vais = 1, reg. x+01h, bit 7 >99.9% ones detected in decoder 1 x 0 ais2vais = 1, reg. x+01h, bit 0 loss of signal on rsyncn 1 1 x lof2vais = 1, reg. x+01h, bit 5
- 61 of 154 - txc-04201b-mb ed. 4, september 2001 ds1mx7 txc-04201b data sheet proprietary transwitch corporation information for use solely by its customers . i = increment bit d = decrement bit n = new data flag bit (enabled = 1001 or 0001/1101/1011/1000, normal or disabled = 0110 or 1110/0010/0100/0111) negative justification: inverted 5 d-bits and accept 8 out of 10 rule positive justification: inverted 5 i-bits and accept 8 out of 10 rule ss-bits (vt size) = 11 for 1544 kbit/s, pointer bytes bit assignment the pointer value is a binary number with a range of 0 to 103 for the 1544 kbit/s format. it indicates the offset from the v2 byte to the first byte in the vt1.5 mapping. the pointer bytes are not counted in the offset calcula- tion. the pointer offset arrangement for this format is shown below. vt/tu pointer offset locations v1 byte v2 byte 1234567812345678 nnnnss-bits ididididid v1 78 79-102 103 v2 0 1-24 25 v3 26 27-50 51 v4 52 53-76 77 1544 kbit/s tu-11/vt1.5
- 62 of 154 - txc-04201b-mb ed. 4, september 2001 proprietary transwitch corporation information for use solely by its customers ds1mx7 txc-04201b data sheet seven independent pointer tracking state machines are used in the ds1mx7. the pointer tracking algorithm is illustrated in figure 28. the pointer tracking state machine is based on the pointer tracking machine found in the latest etsi requirements, and is also valid for both bellcore and ansi. see gr-253-core and g.709 for pointer processing rules. where differences occur the gr-253-core rules are used; in particular, the ais state is not exited to lop state on invalid pointers; receipt of all-ones for a pointer is considered an invalid pointer until 3 consecutive all-ones pointers are received (considered as ais); new pointers without ndf count toward the 3 consecutive new pointers even though an inc/dec action is taken as the result of the new pointer mimicking an inc/dec; the inc/dec decision is 8 out of 10 bits. when control bit sdh (bit 5) in register 007h is set to a 1, the transition from ais to lop is enabled (shown dotted), which is required in itu recommenda- tions. increments and decrements are forwarded to the desynchronizer for counting and use in pointer leak controls as described below. figure 28. vt/tu pointer tracking state machine inc lop ais dec norm 3 x ais_ind (offset undefined) 3 x new_point (accept new offset) 3 x ais_ind (offset undefined) 3 x new_point (accept new offset) 3 x any_point dec_ind (decr. offset) 3 x new_point (accept new offset) 3 x new_point (accept new offset) 3 x any_point ndf_enable (accept new offset) 8 x inv_point (offset undefined) 3 x new_point (accept new offset) 3 x ais_ind (offset undefined) 8 x inv_point (offset undefined) ndf_enable (accept new offset) 3 x ais_ind (offset undefined) 8 x ndf_enable (offset undefined) ndf_enable (accept new offset) ndf_enable (accept new offset) ndf_enable (accept new offset) 3 x new_point (accept new offset) 3 x any_point inc_ind (incr. offset) 3 x ais_ind (offset undefined) ndf
- 63 of 154 - txc-04201b-mb ed. 4, september 2001 ds1mx7 txc-04201b data sheet proprietary transwitch corporation information for use solely by its customers from the telecom bus input, v1 and v2 are extracted by means of dc1j1v1 and dspe. vt/tu lop and vt/ tu ais are individually made available to the microprocessor interface as status bits vaiss and lops (bits 5 and 4) in register x+11h. masks vaism and lopm, latched events vaise and lope, performance values vaispm and loppm and hard fault values vaisfm and lopfm are all bits 5 and 4 of registers x+09h, x+15h, x+19h and x+1dh respectively.the logical ? or ? of these two alarms is handled as ais for the demapped ds1 as described above in the transmit data and signaling highway section. the ? ss ? bits are compared to the expected value of ? 11 ? for a vt1.5/tu-11 and are interpreted as lop (high level signal failure input at pin dfail masks vtais, vtlop and signal label mismatch). the ss-bits are available as status only bits rxss1 and rxss0 (bits 4 and 3) in register x+20h. the demapper the signal label received in the v5 byte is extracted and sent to the microprocessor interface. it is stored in bits 2-0 of register x+20h. additional processing is performed to detect a signal label mismatch (compare with expected signal label) and the unequipped code. both conditions are reported to the microprocessor interface and notification of an unequipped or signal label mismatch condition (also known as vt path label mismatch or plm-v) is handled as described herein for the mapping direction. status bits unes and slms (bits 2 and 1) in register x+11 indicate the current condition. masks unem and slmm, latched events unee and slme, performance values unepm and slmpm and hard fault values unefm and slmfm are all bits 2 and 1 of registers x+09h, x+15h, x+19h and x+1dh respectively. a mismatch alarm is considered as 5 con- secutive signal labels of a different condition; 5 consecutive matches will clear the alarm. the signal label ? equipped - nonspecific ? (001) received is not considered a mismatch to any non-zero expected value. also, if the expected signal label is set to 'equipped-nonspecific' (001) any non-zero value received for the signal label will not cause an alarm. if an unequipped signal label is received, the ds1mx7 will generate an alarm regardless of the setting of the expected signal label (including 000). the alarm should be masked when both ends of a connection are programmed unequipped but a path exists. the table below shows the alarms based on the received versus expected value, per gr-253-core. the v5 and z7/k4 bytes are further processed to extract bip-2 errors, vt/tu rei (febe) events, and vt/tu rdi-v and vt/tu rfi alarms. vt/tu rdi-v is de-bounced for 5 (default) or 10 (selectable) consecutive vt superframes before an alarm is declared; 5 (default) or 10 (selectable) consecutive rdi-v = 0 will clear the alarm. de-bounce control is through global register rdid10 (bit 0) in register 01eh which, when set to a 1, signal label mismatch and unequipped alarms expected signal label stored in reg. x+07h, bits 6-4 received signal label 000 001 010 011 100 101 110 111 000 * m uneq 001 m m 010 m plm 011 plm m plm 100 plm m plm 101 plm m plm 110 plm m plm 111 plm m legend: m = match found and no alarm plm = path label mismatch and alarm, plm-v uneq = unequipped alarm (* ds1mx7 will generate an alarm for rx/exp=000/000)
- 64 of 154 - txc-04201b-mb ed. 4, september 2001 proprietary transwitch corporation information for use solely by its customers ds1mx7 txc-04201b data sheet causes the ds1mx7 to de-bounce all rdi bits over 10 vt superframes. rfi is de-bounced for 10 consecutive vt superframes before an alarm is declared; 10 consecutive rfi = 0 will clear the alarm. v5 byte rdi and rfi alarms are sent to the microprocessor interface once de-bounced, with status bits rfis and rdi-vs (bits 3 and 0) in register x+11h. masks rfim and rdi-vm, latched events rfie and rdi-ve, performance values rfipm and rdi-vpm and hard fault values rfifm and rdi-vfm are all bits 3 and 0 of registers x+09h, x+15h, x+19h and x+1dh respectively. the vt/tu rfi alarm can be sent to the signaling highway as a ds1 yellow for byte-synchronous modes only, as was described in the transmit data and signaling highway sec- tion. bip-2 errors and vt/tu rei (febe) events are accumulated in 12-bit overflow indicating counters. control bit sdh (bit 5) in register 007h, when set to a 1, will cause bip-2 errors to count in blocks (count 1 error if one or both bip-2 bits received is different than calculated). when sdh is set to a 0 each different bit counts as an error. the bip-2 error counter is located at location x+26h and x+27h with a shadow value located at x+2eh and x+2fh. an overflow bit bipos (bit 6) in register x+11h is set to a 1 if an overflow occurs. the rei (febe) error counter is located at location x+28h and x+29h with a shadow value located at x+30h and x+31h. an overflow bit feos (bit 7) in register x+11h is set to a 1 if an overflow occurs. masks bipom and feom, latched events bipoe and feoe, performance values bipopm and feopm and hard fault values bipofm and feofm are all bits 6 and 7 of registers x+09h, x+15h, x+19h and x+1dh respectively. the ds1mx7 supports three-bit rdi using the z7/k4 byte. three-bit rdi is an enhanced remote defect indication that provides three classes of defects: payload defect (path label mismatch), server defects (loss of pointer or ais) and connectivity defects (unequipped). the mechanism uses a combination of v5 bit 0, and z7/k4 bits 3, 2 and 1 to implement an algorithm that is compatible with the existing rdi-v (v5 bit 0) and the new indications. when z7/r4 bits 2 and 1 = 00 or 11, the rdi is from old equipment. when z7/k4 bits 2 and 1 = 01 or 10, the rdi is from enhanced equipment. enhanced rdi is checked for persistency for either 5 or 10 consecutive vt superframes, the same as for rdi-v. alarms are available to the microprocessor interface. status bits rdi-vpds, rdi-vsds and rdi-vcds (bits 2-0) of register x+12h indicate the signals received in z7/k4. masks rdi-vpdm, rdi-vsdm and rdi-vcdm, latched events rdi-vpde, rdi-vsde and rdi-vcde, performance values rdi-vpdpm, rdi-vsdpm and rdi-vcdpm and hard fault values rdi-vpdfm, rdi-vsdfm and rdi-vcdfm are all bits 2 through 0 of registers x+0ah, x+16h, x+1ah and x+1eh respectively. the table below indicates the v5 and z7/k4 bit settings the ds1mx7 uses to support both old equipment and enhanced equipment. higher priority events (e.g., ais) cause rdi codes to be sent that override lower priority rdi codes when both conditions occur simultaneously. the signal failure input pin, dfail, blocks all rdi-v detection. the ds1mx7 will automatically switch between single-bit and three-bit rdi based on the received z7/k4 bits 2 and 1. rdi-v bit settings and interpretation notes: a. these codes are transmitted by equipment that does not support enhanced rdi-v. if enhanced rdi-v is not supported, z7 bits 6 and 7 must be set to the same value. z7/k4 bits 5, 6 and 7 v5 bit 8 priority of enhanced rdi-v codes trigger interpretation yxx a 0 not applicable no defects no rdi-v defect yxx a 1 not applicable ais-v, lop-v, uneq-v b rdi-v defect (one-bit rdi-v) 001 c 0 d 4 no defects no rdi-v defect 010 c 0 d 3 plm-v rdi-v payload defect 101 c 1 d 1 ais-v, lop-v rdi-v server defect 110 c 1 d 2 uneq-v rdi-v connectivity defect
- 65 of 154 - txc-04201b-mb ed. 4, september 2001 ds1mx7 txc-04201b data sheet proprietary transwitch corporation information for use solely by its customers b. a signal label mismatch (plm-v) does not cause a one-bit rdi-v c. this code is transmitted by equipment that supports enhanced rdi-v. d. v5 bit 8 is set to the same value as z7/k4 bit 5 by the equipment that supports enhanced rdi-v. at the receiving equipment, v5 bit 8 is ignored unless z7 bits 6 and 7 are both set to ? 0 ? or both set to ? 1 ? . the signal label expected and the signal label to be sent in the v5 by the ds1mx7 are stored separately in register x+07h. acceptable values for the signal label are as shown in the following table: desynchronization and pointer leak rate calculations desynchronization is performed in two stages, a pointer leak buffer and a dpll/fifo. thus the ds1mx7 removes jitter from the demapped and destuffed vt1.5 or tu-11 in two steps. first the payload is sent to a pointer leak buffer which is a 10-byte deep fifo centered at 5 bytes, allowing for up to 5 vt pointer increments or decrements in a row to be absorbed when a change in a network condition or rate adjustment for byte-syn- chronous mappings are translated into vt pointer movements. the pointer leak buffer converts vt pointer movements ( 8 bits) into slowly leaked single 1 bit adjustments to the dpll/fifo. the pointer leak buffer can be programmed to leak in steps of 8 milliseconds per bit. for test purposes, the pointer leak buffer may be bypassed by setting control bit byplb (bit 4) in register 03dh to a 1. sts-1 pointer movements have approxi- mately one twenty-eighth of the effect of a vt pointer movement; sts-1 pointer movements, in effect, repre- sent about one half of a stuffing bit and are handled by the dpll in the same way as a stuffing bit. the second filtering stage is provided by the dpll, which operates from the ? 31.5 times 1.544 mhz ? clock (48.636 mhz) supplied to pin srclk. the dpll controls a fifo whose depth measurement is made once every vt superframe. from the depth measurement the dpll adjusts its output frequency to match the effects of stuffing performed for asynchronous mapping and pointer movements which have been converted to stuffing by the pointer leak buffer. the dpll provides rate adjustments for byte-synchronous mappings as well as rate adjustments affecting both mappings in addition to asynchronous rate tracking. the dpll has a single pole low pass filter characteristic with a 1.8 hz corner frequency. residual jitter without pointer movement of the demapper is approximately 0.20 ui peak to peak (p-p). mapping and demapping jitter combined with vt pointer movements is under 1.20 ui p-p. through delay (da1 to or from telecom bus) is under 65 ms. for testing purposes the dpll can have its output frequency locked by setting control bit dpllk (bit 7) in glo- bal register 03ch to a 1; control bits dpll6- dpll0 in the same global register are used to adjust the output frequency; this affects all seven channels. when control bit dpllk is set to a 0, control bits dpll6- dpll0 can be used to change the dpll bias offset which changes the dpll fifo ? s residual depth. control register 03ch must be set to 00h for normal desynchronizer operation. since a wide range of vt pointer increment and decrement rates can occur, the ds1mx7 provides a wide range of leak rates. as was mentioned above, the pointer increments and decrements received represent a variety of sources of frequency correction relative to the sonet or sdh clock rates that can occur after a ds1 signal is mapped asynchronously (e.g., due to synchronization failures or clock noise) as well as part of the mapping function for a byte synchronously mapped ds1. a vt pointer movement represents an 8-bit instanta- neous frequency correction (an 8 ui jitter spike). such adjustments are not palatable to most traditional ds1 network equipment and may cause slips or bit errors. the ds1mx7 has a programmable pointer leak buffer vt/tu assignment v5 signal label (bits 5-7) idle/unequipped 000 equipped - nonspecific 001 asynchronous mapping 010 byte-synchronous mapping 100
- 66 of 154 - txc-04201b-mb ed. 4, september 2001 proprietary transwitch corporation information for use solely by its customers ds1mx7 txc-04201b data sheet that can be set to convert the received vt pointer movements to a rate that can match the actual ds1 payload frequency. for example, if a pointer decrement is being received once every second, the ds1 payload signal needs to be adjusted 8 hz higher. by programming the pointer leak buffer to leak one bit every 125 millisec- onds, the dpll will automatically run 8 hz faster continuously by receiving an extra bit in its fifo every 125 milliseconds. if the pointer leak rate is set too slow the pointers will build up in the pointer leak buffer; at a 12 bit (one and a half pointers) level the pointer leak rate automatically doubles to compensate. if the pointer leak rate is set too fast the frequency will be over-corrected for a period and then return to nominal. for example, if the pointer leak rate were set to once every 63 milliseconds for the ? pointer decrement per second ? case, the output frequency would run 16 hz faster (8 hz too high) for one half second and return to nominal (8 hz too low) for one half second. this would cause a frequency modulation of the ds1 output signal that would result in jitter and wander. the mean time interval error (mtie) would build up to an undesirable level relative to gr-253-core objectives and requirements. the table below indicates the pointer leak rate range available by setting per channel control bits pl8 - pl1 in register x+06h. a software-based control loop is required to program the ds1mx7 to meet mtie requirements. the control loop is required to read the received pointer increment and decrement counters, bits 7-4 in register x+24h and bits 3-0 in register x+24h respectively for unlatched values; if the one second performance feature is used by setting control bit enpmfm (bit 3) in register 006h to a 1 and supplying a 1 hz 32 ppm clock on pin t1si, latch pointer increment and decrement values are preferably used from bits 7-4 in register x+2ch and bits 3-0 in register x+2ch respectively. measuring the 4-bit counters every one second is sufficient for up to 15 incre- ments or decrements, representing up to 120 hz, which is beyond the range of a byte-synchronous ds1 used as a clock source (lrclkn as an input) handled between two add drop multiplexers experiencing a syn- chronization failure. to initialize the pointer leak buffer, set it to the maximum expected or possible leak rate required from the application (asynchronous, byte-synchronous, network clock stratum references along the path, etc.). the table below provides some typical settings. from the values that are read, use the net value (increment less decrement) to form a running average over a 30 second period. this value is used to calculate the nearest applicable pointer leak rate for within 12 bits of center and written to the ds1mx7 pl8-pl1 per channel control bits. at each subsequent one-second period, the oldest value is discarded and the newest value is added; the pointer leak rate is again calculated and writ- ten to the ds1mx7 pl8-pl1 control bits. for a constant stream of pointer increments or decrements, the last pointer should be leaked out just before the next pointer arrives. missing or additional pointer increments or pl8 - pl1 time between bits leaked from pointer leak buffer when less than 12 bits from center time between bits leaked from pointer leak buffer when equal to or more than 12 bits from center 00h 16 ms 8 ms 01h 32 ms 16 ms 02h 48 ms 24 ms fdh 4,064 ms 2,032 ms feh 4,080 ms 2,040 ms ffh 4,096 ms 2,048 ms mapping application clock difference pl8 - pl1 asynchronous add drop mux to dcs 38 hz [20 ppm +4.6 ppm] 01h byte-synchronous: lrclkn an output add drop mux to dcs 38 hz [20 ppm +4.6 ppm] 01h byte-synchronous: lrclkn an input add drop mux to dcs with customer ds1 87 hz [20 ppm +4.6 ppm + 32 ppm (ds1 @ stratum 4)] 00h asynchronous dcs to dcs, one stratum 2 7.1 hz [4.6 ppm] 08h asynchronous dcs to dcs, both stratum 3 14.2 hz [9.2 ppm] 04h
- 67 of 154 - txc-04201b-mb ed. 4, september 2001 ds1mx7 txc-04201b data sheet proprietary transwitch corporation information for use solely by its customers decrements in the stream will alter the average only slightly. figure 29 below shows the general algorithm. each time a ds1mx7 is reset, or the channel experiences an ais, lop, ndf or los, the algorithm needs to be restarted. the algorithm is independent for all seven channels and must be performed as such. the maximum range of adjustment due to pointers is when pl8 - pl1 is set to 00h. with at least one and a half residual incre- ments or decrements, one additional or less than normal bit per 8 milliseconds will be sent to the dpll repre- senting, 125 hz. this range supports byte-synchronous mapping for ds1 signals which are 50 hz. figure 29. pointer leak rate algorithm in general, the receive dpll/fifo in the desynchronizer should never overflow or underflow. if it does it will set status bit dmps (bit 6) in register x+10h and recenter the fifo. mask dmpm, latched event dmpe, perfor- mance value dmppm and hard fault value dmpfm are all bit 6 of registers x+08h, x+14h, x+18h and x+1ch respectively. set fifo leak rate to 01 hex (note 3) measure 1 second, add to c (note 4) not 30 seconds 30 seconds calculate fifo leak rate (note 5) start from power on, ais, lop, los, ndf, or reset set fifo leak rate (note 6) measure 1 second (note 6) subtract oldest and add newest (note 7) notes: 1. the procedure described must be performed independently for each of the seven channels. 2. the procedure shown uses a 30-second sliding window with a 1-second resolution. 3. the initial leak rate is application dependent; however setting the pl8 - pl1 value in register x+06h to 01h will cover all a synchronous applica- tions and setting it to 00h will cover all byte-synchronous applications where the ds1 line supplies clock (pleisiochronous). 4. measure 30 consecutive one-second samples from the receive pointer increment and decrement counters. if the counters overflow use a value of 16 for the overflowed counter: s 1 = pointer increment value - pointer decrement value for first one-second sample. s 2 = pointer increment value - pointer decrement value for second one-second sample, and so on. s 30 = pointer increment value - pointer decrement value for thirtieth one-second sample. 5. calculate the leak rate: leak rate = the smaller of (hex [integer {234/c}], hex[int{34/d}] if d > 2, hex[int{25/e}] if e > 2, hex[int{17/f}] if f > 2, hex[int{8/g}] if g > 2) where hex is the hexadecimal value, int is the integer value: c = absolute value [sum(s i to s 30+i )], d = absolute value [sum (s 27+i to s 30+i )], e = absolute value [sum(s 28+i to s 30+i )], f = absolute value [s 29+i + s 30+i ], g = absolute value [s 30+i ], and i represents the number of times through the loop above (notes 5, 6 and 7). if the c is 0 set the leak rate to ffh; a pointer will be leaked before another arrives for uniform pointer arrivals for 0 < c < 234 arrival rates. if d,e,f, or g > 2, faster pointer leaking accounts for a rapid change in pointer arrival rate (e.g. start up after a cool down sequence. 6. set the leak rate register between 1 and 255 per note 5, and take another measurement (e.g., s 31 ). 7. recalculate the value of ? c ? , ? d ? , ? e ? , ? f ? , and ? g ? in note 5 by discarding the oldest value and adding the newest value; (i = i + 1) 8. continue the loop in notes 5, 6 and 7 until the low order path is disrupted (e.g. vtais, vtlop, reset or higher order path f ailure like lop, ais).
- 68 of 154 - txc-04201b-mb ed. 4, september 2001 proprietary transwitch corporation information for use solely by its customers ds1mx7 txc-04201b data sheet jitter measurements equipment used in ds1mx7 jitter measurements: - hewlett packard digital transmission analyzer, hp-3784a - anritsu stm/sonet analyzer, mp1560a - ds1mx7 test fixture jitter tolerance test input jitter tolerance is defined in [gr-499] section 7.3.1 as: the minimum amplitude of sinusoidal jitter at a given frequency that, when modulating the signal at an equip- ment input port, results in more than 2 errored seconds in a 30-second measurement interval. the jitter tolerance is measured by injecting jitter at various frequencies into the ds1mx7 ? s ds1 port by using the hp-3784a as shown in figure 30. the vt1.5 (tu11) mapped data will be monitored on the sonet/sdh side by using the anritsu mp1560a. the jitter tolerance limit of the device is the amount of jitter insertion allowed before a bit error is detected at the point where data is being added to the sonet/sdh data stream. figure 31 shows the jitter tolerance requirements and the measured results for the ds1mx7 device. figure 30. jitter tolerance test setup mp 1560a ds1mx7 hp-3784a 1.544 mbit/s ds1 interface stm/sonet analyzer test fixture digital transmission analyzer sonet data
- 69 of 154 - txc-04201b-mb ed. 4, september 2001 ds1mx7 txc-04201b data sheet proprietary transwitch corporation information for use solely by its customers figure 31. jitter tolerance measurements jitter transfer test for this test the hp-3784a is used to inject a fixed jitter level (1.0 ui) into the ds1 interface of the ds1mx7, as shown in figure 32. the mapped ds1 data is then looped back at the sonet/sdh interface and dropped by the same device. the dropped ds1 jitter is measured at the hp-3784a using a filter of 10hz - 40 khz. the actual jitter transfer measurements for the ds1mx7 device are shown in figure 33. input jitter frequency requirement (ui pp) maximum input jitter (ui pp) f1 10 hz > 5.0 12.0 100 hz > 5.0 7.5 f2 500 hz > 5.0 11.8 1 khz > 1.9 11.5 f3 8 khz > 0.1 11.0 20 khz > 0.1 3.9 f4 40 khz > 0.1 1.9 0.1 1 10 100 10 100 1000 10000 100000 input jitter frequency (hz) input jitter amplitude (ui-pp) maximum tolerated input jitter minimum requirement [gr499] sec. 7.3.1
- 70 of 154 - txc-04201b-mb ed. 4, september 2001 proprietary transwitch corporation information for use solely by its customers ds1mx7 txc-04201b data sheet figure 32. jitter transfer test setup figure 33. jitter transfer measurements input jitter filter used measured output jitter (ui) frequency (hz) unit interval (ui) 10 1.0 (f1 - f4) 0.176 50 1.0 (10 hz -> 40 khz) 0.070 100 1.0 0.052 200 1.0 0.058 600 1.0 0.082 1000 1.0 0.119 ds1mx7 hp-3784a test fixture digital transmission analyzer 0.01 0.1 1 10 10 100 1000 input jitter frequency (hz) ui input measured output
- 71 of 154 - txc-04201b-mb ed. 4, september 2001 ds1mx7 txc-04201b data sheet proprietary transwitch corporation information for use solely by its customers jitter generation the setup shown in figure 34 was used for both the mapping and combined jitter measurements described below. figure 34. jitter generation test setup mapping jitter measurement the following table lists the mapping jitter measurements made with the test setup shown in figure 34 in the absence of sts or vt(tu) pointer adjustments. notes: 1. per recommendation itu-t g.783 (04/97). 2. per bellcore gr-253-core issue 2 dec. 95: rev 2 jan. 99. 3. these values are for further study. interface filter characteristics maximum output jitter (ui pp) requirement measured per g.783 (note 1) per bellcore (note 2) ds1 (f1) (f4) 10 hz -> 40 khz (note 3) 0.7 0.031 (f3) (f4) 10 hz -> 40 khz 0.1 0.7 0.015 anritsu ds1mx7 hp-3784a 1.544 mbit/s ds1 interface stm/sonet analyzer test fixture digital transmission analyzer sonet data mp 1560a
- 72 of 154 - txc-04201b-mb ed. 4, september 2001 proprietary transwitch corporation information for use solely by its customers ds1mx7 txc-04201b data sheet combined jitter measurement this table lists the combined jitter measurements made with the test setup shown in figure 34 with sts-1 and vt 1.5 (tu-11) pointer adjustments as indicated in the first column and shown in figure 35. notes: 1. per recommendation itu-t g.783. 2. per bellcore gr-253-core issue 2 dec. 95: rev 2 jan. 99. 3. these are values written into the desynchronizer pointer leak rate register for mapper port n (register address x+06) normally the pointer leak rate register is controlled by the external microprocessor through the implementation of the pointer leak rate algorithm shown in figure 29. 4. ao is the mapping jitter generated by the device under test. please see mapping jitter measurement on the previous page. pointer test sequence filter leak rate value (hex) (note 3) maximum output jitter (ui pp) requirement measured g.783 (note 1) bellcore (note 2) single pointer adjust- ment = 30 s (f1) (f4) 10 hz -> 40 khz 10h 1.5 ao + 0.60 (note 4) 0.22 periodic vt1.5 pointer adjustment (26-1 pat- tern) = 0.2 s 01h or 02h 1.5 1.3 0.64 periodic vt1.5 pointer adjustment (continuous pattern) = 0.2 s 01h or 02h 1.5 1.3 0.60 periodic vt1.5 pointer adjustment (continuous pattern plus add) = 1 s t = 30 ms 02h 1.5 1.9 0.78
- 73 of 154 - txc-04201b-mb ed. 4, september 2001 ds1mx7 txc-04201b data sheet proprietary transwitch corporation information for use solely by its customers figure 35. standard pointer test sequences measurement period pointer adjustment initialization time 30 s single pointer adjustment test sequence 26 no pointer adjustment start of next 26 - 1 pattern periodic vt1.5 pointer adjustment test sequence (26-1 pattern) periodic vt1.5 pointer adjustment test sequence (continuous pattern) periodic vt1.5 pointer adjustment test sequence (continuous pattern plus add) pointer adjustment added pointer pointer adjustment cool down t
- 74 of 154 - txc-04201b-mb ed. 4, september 2001 proprietary transwitch corporation information for use solely by its customers ds1mx7 txc-04201b data sheet microprocessor interface and common control/status i/o the microprocessor interface and common control/status i/o block allows access and control for each of the seven ds1 mappers. it also provides common control and status of the entire ds1mx7. alarm information detected by the mappers can be read as current status (which may not persist long enough to be easily observed in some cases like counter overflows) and is also latched in event registers which are write to clear. either the arrival or the departure of a condition can be individually enabled to set the event register. to facili- tate either interrupt or polled systems, global interrupt masks, per channel interrupt masks, global event and global polling registers are provided. to assist in the collection of performance parameters, shadow registers and counter latching are provided in addition to latched value and raw value registers. two forms of shadow registers (performance-pm and fault logic-fm) and counter latching are provided at separate locations and are triggered by an external one second clock input pin (t1si), as is described below. the configuration of each mapper is provided by this interface. the serial port control block is also controlled by the microprocessor interface and common control/status i/o. the microprocessor bus supports both intel and motorola style pro- cessors with a minimum amount of interface logic. an external pin (motoi) configures the type of bus sup- ported. the data bus is an 8-bit, bidirectional, 3-state port. the internal control and status registers are accessed through this port. when not accessed, this port is in a high impedance state. the address bus is a 9-bit input port. these address pins select individual control and status registers within the mapper. seli is the microprocessor port select signal. wri and readi /readi/wri are the microprocessor port write and read/ write input pins (only the latter is used for the motorola interface). the rdyo/dtacko output is used to delay microprocessor access, if required to access internal registers. the into/irqo output is the microprocessor port interrupt line. the rsti input is the overall device reset line that resets all counters, state machines and the configuration. pcki is a high speed processor clock input signal that is used by all blocks. alarms the nineteen per channel alarms have been covered in the above sections. to facilitate a quick microprocessor location of an alarm that has been programmed to generate an interrupt, global event and mask registers are provided as well as an activity register. global masks are provided at register locations 015h and 016h. set- ting any of these to a 1 will prevent that condition from generating an interrupt; for example, if the ds1mx7 is programmed for asynchronous operation, setting grfim (bit 3) in register 016h to a 1 would prevent rfi alarms (used in byte-synchronous mappings) from causing spurious interrupts. global event registers are pro- vided at locations 013h and 014h. these registers are the logical ? or ? of all seven like per channel registers; for example, glose (bit 5) in register 013h is the logical ? or ? of all seven lose per channel event registers. note that grdie and grdim provide a global event indication and mask for all rdi conditions (rdi-ve; v5 bit 8 and rdi-vpde, rdi-vsde, rdi-vcde; z7 bits 5, 6 and 7). to facilitate polling, an activity register is provided at location 011h; each bit ch1 to ch7 (bits 0 to 6) represents a mapper channel (1 to 7). each bit chn is the logical ? or ? of all 19 event bits for mapper channel ? n ? . to disable all interrupts to pin into/irqo , control bit gim (bit 7) in register 006h can be set to a 1; polling may be done instead to detect alarm events. the interrupt polarity may be inverted by setting control bit ipol (bit 4) in register 006h to a 1. events may be latched into the event registers (global registers 00ch and 00dh or per channel registers x+14h, x+15h and x+16h) either on the onset of the condition, the exit of the condition or both. control bit rise (bit 6) in register 006h, when set to a 1, will cause the associated event bit to be set when a status bit changes from 0 to 1. likewise, control bit fall (bit 5) in register 006h, when set to a 1, will cause the associ- ated event bit to be set when a status bit changes from 1 to 0. by setting both rise and fall to a 1, both the onset of an alarm and the clearing of an alarm will cause an interrupt if the event register is cleared after the onset of the alarm. assuming all mask bits are set to a 0, asynchronous mode is used, and both rise and fall are set to a 1, the following scenario would apply if mapper channel 2 (x=080h) detected a los condition for 2 seconds at its line decoder. first, bit 5 of register 090h (loss) would be set to a 1. bit 5 of register 094h (lose) would be set to a 1 on the rising edge of loss. this would set bit 5 of register 013h (glose) to a 1, set bit 1 of register 011h (ch2) to a 1 and cause an interrupt to be asserted on pin into/irqo . the software in the attached microprocessor would respond by reading registers 011h, 013h and 014h. analysis would indicate an los
- 75 of 154 - txc-04201b-mb ed. 4, september 2001 ds1mx7 txc-04201b data sheet proprietary transwitch corporation information for use solely by its customers change at channel 2. the software in the attached microprocessor would then respond by reading registers 090h and 094h, followed by clearing register 094h by writing 00h to it. this writing to clear will automatically clear the interrupt, bit 5 of register 013h (glose) and bit 1 of register 011h (ch2). at the end of 2 seconds, bit 5 of register 090h (loss) will clear. bit 5 of register 094h (lose) would be set on the falling edge of loss. this would set bit 5 of register 013h (glose) to a 1, set bit 1 of register 011h (ch2) to a 1 and cause an inter- rupt to be asserted on pin into/irqo . the software in the attached microprocessor would respond by reading registers 011h, 013h and 014h. analysis would indicate an los change at channel 2. the software in the attached microprocessor would then respond by reading registers 090h and 094h followed by clearing register 094h by writing 00h to it. this writing to clear will automatically clear the interrupt, bit 5 of register 013h (glose) and bit 1 of register 011h (ch2). to provide for operational security and fault localization, system clocks and reference signals are optionally monitored for lack of transitions and alarmed to the microprocessor interface and the internal alarm output in iao . status bits tbrcks, tbrsns and tbrpas (bits 7 through 5) in register 00ah indicate a failure of dclk, dc1j1v1 or dspe, if set to a 1, respectively. mask bits mtbrcf, mtbrsf and mtbrpf, latched event bits tbrcke, tbrsne and tbrpae, performance values tbrckpm, tbrsnpm and tbrpapm, and fault val- ues tbrckfm, tbrsnfm and tbrpafm are all bits 7, 6 and 5 of registers 008h, 00ch, 00eh and 03eh respectively. status bits tbtcks, tbtsns and tbtpas (bits 2 through 0) in register 00ah indicate a failure of aclk, ac1j1v1 or aspe, if set to a 1, respectively. mask bits mtbtcf, mtbtsf and mtbtpf, latched event bits tbtcke, tbtsne and tbtpae, performance values tbtckpm, tbtsnpm and tbtpapm, and fault values tbtckfm, tbtsnfm and tbtpafm are all bits 2 through 0 of registers 008h, 00ch, 00eh and 03eh respectively. status bit mcks (bit 3) in register 00ah indicates a failure of srclk if set to a 1. mask bit mmckf, latched event bit mcke, performance value mckpm, and fault value mckfm are all bit 3 of registers 008h, 00ch, 00eh and 03eh respectively. in addition, internal checks are made in the telecom bus interface block to determine if two or more channels of a ds1mx7 device attempt to drive the same bus slot; if multiple channel drive attempts are detected an internal alarm event is indicated by status bit tbies (bit 1) in register 00bh being set to a 1. mask bit mtbie, latched event bit tbiee, performance value tbiepm, and fault value tbiefm are all bit 1 of registers 009h, 00dh, 00fh and 03fh respectively. similarly, if two or more ds1mx7s attempt to drive the telecom bus simul- taneously, an external alarm is declared by status bit tbxes (bit 0) in register 00bh being set to a 1; this is implemented by connecting the aadd output of each ds1mx7 to one of the three buschk inputs of the other ds1mx7s (up to 4 ds1mx7s are supported without external logic). mask bit mtbxe, latched event bit tbxee, performance value tbxepm, and fault value tbxefm are all bit 0 of registers 009h, 00dh, 00fh and 03fh respectively. parity errors are monitored on the drop telecom bus for all active slots from which signals are dropped. control bit tbpis (bit 3) in register 007h includes dc1j1v1 and dspe in the parity check if set to a 1. control bit tbpe (bit 2) in the same register selects even parity if set to a 1. status bit tbrpys (bit 3) in reg- ister 00bh is set to a 1 whenever a parity error is detected. mask bit mtbrpy, latched event bit tbrpye, per- formance value tbrpypm, and fault value tbrpyfm are all bit 3 of registers 009h, 00dh, 00fh and 03fh respectively. bad parity may be forced onto the add telecom bus by setting control bit ftbtpe (bit 6) in regis- ter 01eh to a 1. device alarms can also be enabled to a separate alarm output pin iao , which can be used as an interrupt or a board failure lead when wire "or" gated with other ds1mx7s. control bits etbrcf, etbrsf, etbrpf (bits 7 through 5) in register 01bh, when set to a 1, enable the dclk, dc1j1v1 and dspe failures to drive pin iao low. control bits etbtcf, etbtsf, etbtpf (bits 2 through 0) in register 01bh, when set to a 1, enable the aclk, ac1j1v1 and aspe failures to drive pin iao low. likewise, emckf (bit 3) in register 01bh, when set to a 1, enables the srclk failure to drive pin iao low. control bits etbrpy, etbie, etbxe (bits 3, 1 and 0) in register 01ch, when set to a 1, enable the parity error, internal telecom bus collision and external telecom bus collision to drive pin iao low. the alarm output iao is enabled by control bit enhwm (bit 2) in register 006h being set to a 1. to provide for masking alarms on a particular assigned vt/tu, the dfail input pin signal, which indicates a general signal failure, is sampled on the rising edge of dclk and latched for the particular channel assigned to
- 76 of 154 - txc-04201b-mb ed. 4, september 2001 proprietary transwitch corporation information for use solely by its customers ds1mx7 txc-04201b data sheet that vt/tu column. if it is high, the data on dd(0-7) is invalid (e.g., sts-1 ais), and any alarms generated as a result will not interrupt the microprocessor. however, some consequent actions on the data should still be properly handled (e.g., generate ds1 ais); other actions (e.g., rdi) will not occur. dfail is not included in bus parity. the following tables show the masking of lower order alarms by higher order alarms provided in the ds1mx7 in both the mapping and demapping directions. ds1mx7 demapper alarm masking the shaded area indicates which detectors are blocked for which condition. for example, vt ais blocks vt lop, vt unequipped, signal label mismatch, vt rdi, vt rfi and demap errors. ds1mx7 demapper alarm masking figure 36 illustrates the operation of the shadow registers for a loss of signal (loss) alarm for any one of the seven mappers. the behavior shown in the diagram also applies to the other alarms in the same registers (ais, lop, rdi, etc.) for per channel alarms. global control bit enpmfm (bit 3) in register 006h is assumed to be set to a 1. global alarms (e.g., master clock fail - mcks, mcke, etc.) are handled slightly differently in that the t1si pulse does not clear the event value as it does for per channel alarms. this figure assumes that con- trol bits rise and fall (bits 6 and 5) in the global configuration register 006h are set to 10 (latched event set on a positive transition only). please note that the los alarm causes a latched status indication lose (bit 5) in register x+14h, and that the latched bit is reset by the rising edge of the t1si pulse. the lospm status bit (bit 5) in register x+18h is a 1 whenever there is a transition to los during the last one-second interval or los is present at the end of the last one-second interval. the losfm status bit (bit 5) in register x+1ch is a 1 if the los alarm is active but did not become active during the previous one-second interval. condition reported signal fail vt ais detected vt lop detected vt unequipped detected signal label mismatch detected vt rdi detected vt rfi detected demap error signal failure x vt ais x vt lop x vt uneq. x sig label mismatch x vt rdi x vt rfi x demap error x condition los ais oof yellow map error los x ds1 ais x oof x other
- 77 of 154 - txc-04201b-mb ed. 4, september 2001 ds1mx7 txc-04201b data sheet proprietary transwitch corporation information for use solely by its customers figure 36. shadow register operation serial port control interface the serial port control interface block is a serial interface that can be used to control and manage the external analog line transceivers operating in the ? host mode ? . this allows the system processor to have complete con- trol of the line transceivers through the ds1mx7 microprocessor interface. the interface consists of a data input pin (lsdi), a data output pin (lsdo), and a serial clock output pin (lsclk) that are shared among all the transceivers. the source of lsclk is the signal present on input pin lo. in addition, there is an individual chip select (lcsn ) for each transceiver, and an individual input (laisn) from each transceiver that may be used to generate a maskable interrupt; status bit xps (bit 7) in register x+10h indicates the signal on this pin. a mask xpm, a latched event value xpe, a pm value xppm and a fm value xpfm are available (bit 7) at register loca- tions x+08h, x+14h, x+18h and x+1ch respectively. if desired, the signal at this pin may be used to indicate a loss of signal, which can be used to generate ais (see the line interface section for details). data to be written to the external transceiver is formatted as a two-byte message. the first byte is an address/ command byte and the second byte contains the data to be written or read. figure 37 illustrates the message and control formats associated with the transceiver serial i/o timing. the format of the address/command byte depends upon the external transceiver being controlled. please refer to the transceiver's data sheet for the command/data formats. the interface for controlling the external transceiver operates in the following way. the external transceiver selection (via lcsn ) is determined by the value written to three bits (bits 2, 1 and 0) in reg- ister 01ah. for example, a 000 value selects the transceiver for mapper 1. the microprocessor writes the com- mand byte to the line interface control register 017h. this is followed by writing the data byte to be written to t1si loss lose lospm losfm t=0 sec t=1 sec t=2 sec t=3 sec t=4 sec t=5 sec t=6 sec (bit 5 in x+1ch) (bit 5 in x+18h) (bit 5 in x+14h) (bit 5 in x+10h) note 1: for this example, latched events are set only on positive event transitions. note 2: lospm = loss + lose evaluated at one-second boundaries (where ? + ? is a logical or). note 3: losfm = loss & lose evaluated at one-second boundaries (where ? & ? is a logical and, and x is a logical inversion).
- 78 of 154 - txc-04201b-mb ed. 4, september 2001 proprietary transwitch corporation information for use solely by its customers ds1mx7 txc-04201b data sheet the selected transceiver in line interface control register 018h. the serial message is sent on lsdo when a 1 is written to replace the 0 in the ensrp bit (bit 4) in register 01ah. the ensrp bit must be first written with a 0, followed by a 1, before another transfer can take place between the ds1mx7 and the external transceiver selected. broadcast capability to all transceivers is enabled when the control bit bdcst (bit 7) in register 01ah is written with a 1. eight clock cycles later, the selected transceiver will respond by sending serial data on the lsdi input pin. the data is shifted in to the serial port data input register 019h, lsb first. . figure 37. serial interface operation ds1mx7 channel testing using the prbs generator and analyzer the prbs generator and analyzer block provides the ability to test each channel using the tributary and/or telecom bus loopback features provided. figure 38 below shows the general configuration used for testing any one of the seven channels. control bit tblpbk (bit 7) in register 01eh, when set to a 1, loops back the tele- com bus. setting tblpbk to a 1 should only be done if all seven channels are off line, because normal opera- tion for the channels not under test is suspended. for the telecom bus loopback to function, control bits in registers x+04h and x+05h also need to be set to enable the vt1.5/ tu-11 to and from the same telecom bus slot. control bit dtlpbk (bit 7) in register x+0ch, when set to a 1, loops the line coder output clock, sig- naling, synchronization pulse and data back to the line decoder input, providing a local loopback. this ds1 tributary loopback can only be used in the asynchronous and modified byte synchronous modes. the local loopback can be moved to the line interface transceiver or as a distant end remote loop back. it should be noted that if ais is to be sent to the line during a local loopback, it must be provided externally to the ds1mx7 (e.g., via a qt1f- plus or liu). if the distant end is a ds1mx7, control bit dflpbk (bit 6) in register x+0ch may be set to a 1 to loop the received ds1 clock, signaling, synchronization and data to the transmit clock, sig- naling, synchronization and data. the prbs pattern may be inserted into any one or more mappers in place of the line decoder output by setting control bit sprbs (bit 4) in register x+0ch to a 1 when control bit eprbsa (bit 5) in global register 01ah is also set to a 1. the prbs analyzer is assigned to a mapper channel by the same control bits used to select an liu for the serial port, bits 2-0 in register 01ah. the analyzer monitors any one of the seven line decoder outputs. the output of the analyzer is readable by the microprocessor interface as status bit prbss (bit 2) in register 00bh with a mask mprbse, a latched value prbse, a performance value prbspm and a hard fault value prbsfm, all bit 2 in registers 009h, 00dh, 00fh and 03fh respec- tively. the pattern is a 2 15 -1 bit pseudo-random binary sequence that follows the itu o.151 recommendations, but is inverted. control bit txnrzp (bit 0) in register 007h, when set to a 1, will make the internal prbs signal readable by standard test equipment connected to the ds1 line side of the ds1mx7 mapper channel. the out of lock alarm can be made to go to an external pin iao , if desired, by setting control bit eprbse, bit 2 in reg- ister 01ch, to a 1. lcsn lsclk lsdo lsdi addr d0 d1 d2 d3 d4 d5 d6 d7 r/w addr addr addr addr addr addr data input/output address/command byte d0 d1 d2 d3 d4 d5 d6 d7
- 79 of 154 - txc-04201b-mb ed. 4, september 2001 ds1mx7 txc-04201b data sheet proprietary transwitch corporation information for use solely by its customers figure 38. loopbacks and built-in prbs testing of the ds1mx7 telecom bus interface the telecom bus interface contains the drivers and receivers for all the telecom bus signals. it multiplexes and demultiplexes all the data flowing from/to the telecom bus output and input control blocks. it also calculates the parity for apar and checks the parity against dpar for any driven slot used by this ds1mx7 (both odd and even parity are selectable, and apar may be calculated on ad(0-7) only or on the combination of ad(0-7), aspe and ac1j1v1); slots that are not selected are skipped. telecom bus assignments can be used to local- ize parity errors. this block generates the aadd signal for any active slot driven by this ds1mx7, to permit using external buffers. aadd is generally not required as the ds1mx7 outputs are tristated; however, if an application requires bus drivers with different characteristics or with additional drive this signal is available. spe is valid during the sts-1 or sts-3 synchronous payload. c1j1v1 defines the starting position of the vt/ tus on the bus. note that ad(0-7) data is pre-fetched to be ready to be clocked into an external device on the rising edge of aclk; if the column or byte is a stuff position in the sts-1 the data remains present until the slot is a valid spe (aspe active). for systems that use the telecom bus to multiplex in transport or path overhead information (e.g., h4 via the transwitch sot-1e), the daten pin should be tied externally to aspe so that spe inactive bytes are not driven during the rising edge of aclk. when the ad(0-7) signals are delayed one aclk clock period by control bit tbdd (bit 3) in register 01eh, the aspe signal into the daten must be delayed by one aclk clock period to align with the data output to the add bus. if required, the master input pin may be grounded so that the sts-1 poh and stuff columns or bytes may be driven with idle (all-zeros with valid parity) or an assigned vt value such that bus parity errors are prevented. the following table shows which bytes are driven on the telecom bus in various modes; note that each sts-1 or tug-3 is treated sepa- rately. under microprocessor interface control the data, ad(0-7), may be delayed one clock period by control bit tbdd (bit 3) in register 01eh, and the active clock edges of dclk and aclk may be inverted by control bits tbrci (bit 4) and tbtci (bit 5) in the same register being set to a 1. ds1 line line coder line decoder one of seven mapper channels dflpbk sprbs dtlpbk prbs gen. 1 0 1 1 0 0 demapper desynch. mapper synch. telecom bus i/f tblpbk 0 1 prbs anal. te l e c o m b u s prbss note: control and status bits are shown in bold font 1 0 sdaisl ais
- 80 of 154 - txc-04201b-mb ed. 4, september 2001 proprietary transwitch corporation information for use solely by its customers ds1mx7 txc-04201b data sheet . the telecom bus interface also provides a loopback mode for device testing. internally, the entire telecom bus is looped. individual channels are tested by enabling them through the serial port select byte for the prbs analyzer and the per channel select bit for the prbs generator, as described above. the mapper timing block supplies overall mapper timing to both the synchronizer/mapper and the desynchro- nizer/demapper blocks based on the telecom bus clocks, c1j1v1 and spe signals received. sonet and sdh have different stuff column positions. in sonet format v1 is coincident with v1 #1; in sdh format for tug-3, v1 starts six tug-3 clock pulses early. a bit in the common control register is used to select this. the external clock, lo, is an independent 1.544 mhz clock for the purpose of generating a system-synchronized clock for clocking in data and signaling for byte-synchronous operation. the ds1mx7 can operate at 6.48 mhz or 19.44 mhz, as shown in figures 39 and 40. the bus speed is deter- mined by the configi pin; if tied low, the ds1mx7 operates in 19.44 mhz mode with 84 vt1.5/ tu-11 slots; if tied high, the ds1mx7 operates in 6.48 mhz mode with 28 vt1.5/ tu-11 slots. for gapped clock situations an allowance for up to 10% higher speed needs to be made. the ds1mx7 cannot account for extra columns, so spe being inactive for extra columns must be used. for 19.44 mhz operation in sonet or sdh au-3 mapping, the three j1 signals can be anywhere in the sts-1 or au-3 for both dc1j1v1 and ac1j1v1; hence separate tracking is provided for each. control bit vc3vc4 (bit 1) in register 007h must be set to a 1. in this mode of operation there are no restrictions on the three j1 positions in ac1j1v1 for asynchronous or modified byte-synchronous applications. however, if byte-synchro- nous modes are used, the three j1s in ac1j1v1 cannot move with respect to each other, since lo must be locked to aclk and ac1j1v1. if all channels are mapped to a specific sts-1, the restriction does not apply as long as the j1 reference for lo is the same sts-1. daten and master pins assigned vt unassigned vt poh and stuff toh toh condition followed by assigned vt followed by poh or stuff daten high; master high driven aadd low float aadd high float aadd high driven to vt value that fol- lows aadd low float aadd high daten high; master low driven aadd low float aadd high driven to zero aadd high driven to vt value that fol- lows aadd low driven to zero aadd high daten = aspe; master high (see note) driven aadd low float aadd high float aadd high float aadd high float aadd high daten = aspe; master low (see note) driven aadd low float aadd high driven to zero aadd high float aadd high float aadd high daten low float aadd high float aadd high float aadd high float aadd high float aadd high note: the aspe signal into the daten input must be delayed by one aclk clock period when the telecom bus data delay, control bit tbdd (bit 3 in register 01eh) is enabled.
- 81 of 154 - txc-04201b-mb ed. 4, september 2001 ds1mx7 txc-04201b data sheet proprietary transwitch corporation information for use solely by its customers figure 39. telecom bus structure; sonet or vc-3 sdh; telecom bus @ 6.48 mhz the signals shown in figure 39 are valid for the entire sts-1 signal, representing an overlay of all 36 rows of 90 bytes each. each of the 28 vt1.5s occupy 3 columns (counted from the sts-1 path overhead and with the two stuff columns the same) with transport overhead (toh) taking 3 columns (shaded), the sts-1 path over- head taking a column (j1, b3.z5) and 2 columns of fixed stuff (crosshatched). spe is only low during toh. c1j1v1 is high during the 4 c1 bytes shown, the 4 j1 bytes shown and the one v1 #1 byte shown. for vt#1 of vtg#1, j2, z6 and z7 are also shown. figure 41 below provides the column assignments for an sts-1 system bus. the sts-3 case is as depicted in figure 40, with the columns of the three sts-1s byte-interleaved; in this case, the three c1 bytes occur together, but the individual j1 bytes can occur in any of the 87 columns of the sts-1 or vc-3. fixed offset places v5s after v1s. figure 42 below provides the column assignments for the sts-3. c1 c1 c1 c1 h1h2h3 v1. . . . . . . . . . .v1 v2. . . . . . . . . . .v2 v3. . . . . . . . . . .v3 v4. . . . . . . . . . .v4 v5 v5 i v5 v1v1v1. . . . . . . . . . . . .v1v1 j1 v2v2v2. . . . . . . . . . . . .v2v2 j1 v3v3. . . . . . . . . . . . .v3v3 j1 v4v4v4. . . . . . . . . . . . .v4v4 j1 z6 j2 v5 v5 z7 b3 c2 g1 f2 h4 z4 z5 z3 d j 1 v 1 # 1 spe c1j1v1 clk c 1 1 36 1 90
- 82 of 154 - txc-04201b-mb ed. 4, september 2001 proprietary transwitch corporation information for use solely by its customers ds1mx7 txc-04201b data sheet figure 40. telecom bus structure; tug-3 sdh; telecom bus @ 19.44 mhz figure 40 above shows the sdh format for three tug-3s in a vc-4. control bit vc3vc4 (bit 1) in register 007h must be set to a 0. figure 43 below provides the column assignments for an stm-1. each tug-3 contains seven tug-2s and each tug-2 contains four tu-11s. the signals shown are an overlay of all 36 rows of 270 bytes each. spe is low only for the stm-1 transport overhead (toh), which is the first 9 columns (shaded). c1j1v1 is high for the first c1 byte of the toh, the j1 byte of the vc-4 path overhead (poh) and the first col- umn of each tug-3 (null pointer indications). fixed offset for v5 generation of 78 places system-bound v5 bytes after v1 bytes for asynchronous only. in the byte-synchronous mode (modified byte-synchronous or true byte-synchronous operation), the initial location of the v5 bytes is defined by the phase between the add bus reference, ac1j1v1, and rsyncn. if the relationship changes slowly, v1 and v2 are incremented or decre- mented to track the signal. abrupt changes in rsyncn will cause a new value of v1 and v2 to be generated with a corresponding ndf indication in v1. c1c1c1 j1 b3 c2 g1 f2 h4 z3 z4 z5 n p i n p i n p i v1v1v1. . . . . . . . . . . .v1 v5 v5 #1 #2 #3. . . . . . . . . . . . #3 # # # 1 2 3 # # # 1 2 3 c1c1c1 1 270 v2v2v2. . . . . . . . . . . .v2 #1 #2 #3. . . . . . . . . . . . #3 v5 v5 v5 spe j 1 v c1j1v1 c 1 36 1 1
- 83 of 154 - txc-04201b-mb ed. 4, september 2001 ds1mx7 txc-04201b data sheet proprietary transwitch corporation information for use solely by its customers multiplex format and mapping information sts-1 vt1.5 (1.544 mbit/s) multiplex format the following diagram and table illustrate the mapping of the 28 vt1.5s into a sts-1 spe. column 1 is assigned to carry the path overhead bytes. figure 41. sts-1 spe mapping 1 2 3 27 123 4 27 vt vt vt vt vt 3 columns 1315987 1.5 # 28 1.5 #2 1.5 # 28 1.5 #1 1.5 # 28 vt vt vt vt 1.5 #1 1.5 #2 1.5 #1 1.5 #2 30 29 58 60 vt1.5 r r r r r r r r r j1 b3 c2 g1 f2 h4 z3 z4 z5 sts-1 spe r r r r r r r r r
- 84 of 154 - txc-04201b-mb ed. 4, september 2001 proprietary transwitch corporation information for use solely by its customers ds1mx7 txc-04201b data sheet sts-1 mapping vt# registers x+04h for drop and x+05h for add vt1.5 column numbers* 76543210 0xxxxxxx no vt selected 1 10000000 2, 31, 60 2 10000100 3, 32, 61 3 10001000 4, 33, 62 4 10001100 5, 34, 63 5 10010000 6, 35, 64 6 10010100 7, 36, 65 7 10011000 8, 37, 66 8 10000001 9, 38, 67 9 10000101 10, 39, 68 10 10001001 11, 40, 69 11 10001101 12, 41, 70 12 10010001 13, 42, 71 13 10010101 14, 43, 72 14 10011001 15, 44, 73 15 10000010 16, 45, 74 16 10000110 17, 46, 75 17 10001010 18, 47, 76 18 10001110 19, 48, 77 19 10010010 20, 49, 78 20 10010110 21, 50, 79 21 10011010 22, 51, 80 22 10000011 23, 52, 81 23 10000111 24, 53, 82 24 10001011 25, 54, 83 25 10001111 26, 55, 84 26 10010011 27, 56, 85 27 10010111 28, 57, 86 28 10011011 29, 58, 87 * note: columns 30 and 59 carry fixed stuff bytes. column 1 is assigned for the poh bytes.
- 85 of 154 - txc-04201b-mb ed. 4, september 2001 ds1mx7 txc-04201b data sheet proprietary transwitch corporation information for use solely by its customers sts-3/au-3 vt1.5/tu-11 (1.544 mbit/s) multiplex format mapping the following diagram and table illustrate the mapping of the vt1.5/tu-11s into a sts-3/au-3 spe. each sts-3 carries three sts-1s. column 1 in each sts-1/au-3 is assigned to carry the path overhead bytes. figure 42. sts-3/au-3 mapping sts-1 #1 #2 #3 sts-3/au-3 spe 1 2 3 27 12 3 4 27 vt vt vt vt vt vt 1 261 3 columns 13159 871 87 j1 b3 c2 g1 f2 h4 z3 z4 z5 j1 b3 c2 g1 f2 h4 z3 z4 z5 j1 b3 c2 g1 f2 h4 z3 z4 z5 1.5 # 28 1.5 #2 1.5 # 28 1.5 # 28 vt vt vt vt vt vt vt 1.5 #1 1.5 #2 1.5 #1 1.5 #2 1.5 #1 1.5 #2 1.5 # 28 1.5 #1 1.5 #2 30 29 58 60 1 vt1.5 3 r r r r r r r r r r r r r r r r r r 2 vt 1.5 #1 87 vt 1.5 # 28
- 86 of 154 - txc-04201b-mb ed. 4, september 2001 proprietary transwitch corporation information for use solely by its customers ds1mx7 txc-04201b data sheet sts-3 au-3 mapping * note: columns 88, 89, 90, 175, 176, 177 are fixed stuff. vt tu # registers x+04h or x+05h 6 5 4 3 2 1 0 vt/tu column numbers vt tu # registers x+04h or x+05h 6 5 4 3 2 1 0 vt/tu column numbers vt tu # registers x+04h or x+05h 6 5 4 3 2 1 0 vt/tu column numbers* tbtval or tbrval = 0 no tu selected 1 0 0 0 0 0 0 0 4 91 178 29 0 1 0 0 0 0 0 5 92 179 57 1 0 0 0 0 0 0 6 93 180 2 0 0 0 0 1 0 0 7 94 181 30 0 1 0 0 1 0 0 8 95 182 58 1 0 0 0 1 0 0 9 96 183 3 0 0 0 1 0 0 0 10 97 184 31 0 1 0 1 0 0 0 11 98 185 59 1 0 0 1 0 0 0 12 99 186 4 0 0 0 1 1 0 0 13 100 187 32 0 1 0 1 1 0 0 14 101 188 60 1 0 0 1 1 0 0 15 102 189 5 0 0 1 0 0 0 0 16 103 190 33 0 1 1 0 0 0 0 17 104 191 61 1 0 1 0 0 0 0 18 105 192 6 0 0 1 0 1 0 0 19 106 193 34 0 1 1 0 1 0 0 20 107 194 62 1 0 1 0 1 0 0 21 108 195 7 0 0 1 1 0 0 0 22 109 196 35 0 1 1 1 0 0 0 23 110 197 63 1 0 1 1 0 0 0 24 111 198 8 0 0 0 0 0 0 1 25 112 199 36 0 1 0 0 0 0 1 26 113 200 64 1 0 0 0 0 0 1 27 114 201 9 0 0 0 0 1 0 1 28 115 202 37 0 1 0 0 1 0 1 29 116 203 65 1 0 0 0 1 0 1 30 117 204 10 0 0 0 1 0 0 1 31 118 205 38 0 1 0 1 0 0 1 32 119 206 66 1 0 0 1 0 0 1 33 120 207 11 0 0 0 1 1 0 1 34 121 208 39 0 1 0 1 1 0 1 35 122 209 67 1 0 0 1 1 0 1 36 123 210 12 0 0 1 0 0 0 1 37 124 211 40 0 1 1 0 0 0 1 38 125 212 68 1 0 1 0 0 0 1 39 126 213 13 0 0 1 0 1 0 1 40 127 214 41 0 1 1 0 1 0 1 41 128 215 69 1 0 1 0 1 0 1 42 129 216 14 0 0 1 1 0 0 1 43 130 217 42 0 1 1 1 0 0 1 44 131 218 70 1 0 1 1 0 0 1 45 132 219 15 0 0 0 0 0 1 0 46 133 220 43 0 1 0 0 0 1 0 47 134 221 71 1 0 0 0 0 1 0 48 135 222 16 0 0 0 0 1 1 0 49 136 223 44 0 1 0 0 1 1 0 50 137 224 72 1 0 0 0 1 1 0 51 138 225 17 0 0 0 1 0 1 0 52 139 226 45 0 1 0 1 0 1 0 53 140 227 73 1 0 0 1 0 1 0 54 141 228 18 0 0 0 1 1 1 0 55 142 229 46 0 1 0 1 1 1 0 56 143 230 74 1 0 0 1 1 1 0 57 144 231 19 0 0 1 0 0 1 0 58 145 232 47 0 1 1 0 0 1 0 59 146 233 75 1 0 1 0 0 1 0 60 147 234 20 0 0 1 0 1 1 0 61 148 235 48 0 1 1 0 1 1 0 62 149 236 76 1 0 1 0 1 1 0 63 150 237 21 0 0 1 1 0 1 0 64 151 238 49 0 1 1 1 0 1 0 65 152 239 77 1 0 1 1 0 1 0 66 153 240 22 0 0 0 0 0 1 1 67 154 241 50 0 1 0 0 0 1 1 68 155 242 78 1 0 0 0 0 1 1 69 156 243 23 0 0 0 0 1 1 1 70 157 244 51 0 1 0 0 1 1 1 71 158 245 79 1 0 0 0 1 1 1 72 159 246 24 0 0 0 1 0 1 1 73 160 247 52 0 1 0 1 0 1 1 74 161 248 80 1 0 0 1 0 1 1 75 162 249 25 0 0 0 1 1 1 1 76 163 250 53 0 1 0 1 1 1 1 77 164 251 81 1 0 0 1 1 1 1 78 165 252 26 0 0 1 0 0 1 1 79 166 253 54 0 1 1 0 0 1 1 80 167 254 82 1 0 1 0 0 1 1 81 168 255 27 0 0 1 0 1 1 1 82 169 256 55 0 1 1 0 1 1 1 83 170 257 83 1 0 1 0 1 1 1 84 171 258 28 0 0 1 1 0 1 1 85 172 259 56 0 1 1 1 0 1 1 86 173 260 84 1 0 1 1 0 1 1 87 174 261 sts-1 #1, au-3 a sts-1 #2, au-3 b sts-1 #3, au-3 c
- 87 of 154 - txc-04201b-mb ed. 4, september 2001 ds1mx7 txc-04201b data sheet proprietary transwitch corporation information for use solely by its customers tu-11 - vc-4 multiplex format mapping the following figure 43 and table illustrate the mapping of tu-11s into a vc-4. figure 43. stm-1/vc-4 mapping 1 2 3 27 123 4 27 2 3 4 2 3 4 2 3 4 67 2 712 7 n p i n p i 7 n p i 1 p o h 1 261 3 columns tu-11 tug-2 tug-3 13159 86186 vc-4 86 1 11 11 3 7 1 1 10 4
- 88 of 154 - txc-04201b-mb ed. 4, september 2001 proprietary transwitch corporation information for use solely by its customers ds1mx7 txc-04201b data sheet tu-11 - vc-4 multiplex format mapping tu # registers x+04h or x+05h 6 5 4 3 2 1 0 vc-4 column numbers tu # registers x+04h or x+05h 6 5 4 3 2 1 0 vc-4 column numbers tu # registers x+04h or x+05h 6 5 4 3 2 1 0 vc-4 column numbers tbtval or tbrval = 0 no tu selected 1 0 0 0 0 0 0 0 10 94 178 29 0 1 0 0 0 0 0 11 95 179 57 1 0 0 0 0 0 0 12 96 180 2 0 0 0 0 1 0 0 13 97 181 30 0 1 0 0 1 0 0 14 98 182 58 1 0 0 0 1 0 0 15 99 183 3 0 0 0 1 0 0 0 16 100 184 31 0 1 0 1 0 0 0 17 101 185 59 1 0 0 1 0 0 0 18 102 186 4 0 0 0 1 1 0 0 19 103 187 32 0 1 0 1 1 0 0 20 104 188 60 1 0 0 1 1 0 0 21 105 189 5 0 0 1 0 0 0 0 22 106 190 33 0 1 1 0 0 0 0 23 107 191 61 1 0 1 0 0 0 0 24 108 192 6 0 0 1 0 1 0 0 25 109 193 34 0 1 1 0 1 0 0 26 110 194 62 1 0 1 0 1 0 0 27 111 195 7 0 0 1 1 0 0 0 28 112 196 35 0 1 1 1 0 0 0 29 113 197 63 1 0 1 1 0 0 0 30 114 198 8 0 0 0 0 0 0 1 31 115 199 36 0 1 0 0 0 0 1 32 116 200 64 1 0 0 0 0 0 1 33 117 201 9 0 0 0 0 1 0 1 34 118 202 37 0 1 0 0 1 0 1 35 119 203 65 1 0 0 0 1 0 1 36 120 204 10 0 0 0 1 0 0 1 37 121 205 38 0 1 0 1 0 0 1 38 122 206 66 1 0 0 1 0 0 1 39 123 207 11 0 0 0 1 1 0 1 40 124 208 39 0 1 0 1 1 0 1 41 125 209 67 1 0 0 1 1 0 1 42 126 210 12 0 0 1 0 0 0 1 43 127 211 40 0 1 1 0 0 0 1 44 128 212 68 1 0 1 0 0 0 1 45 129 213 13 0 0 1 0 1 0 1 46 130 214 41 0 1 1 0 1 0 1 47 131 215 69 1 0 1 0 1 0 1 48 132 216 14 0 0 1 1 0 0 1 49 133 217 42 0 1 1 1 0 0 1 50 134 218 70 1 0 1 1 0 0 1 51 135 219 15 0 0 0 0 0 1 0 52 136 220 43 0 1 0 0 0 1 0 53 137 221 71 1 0 0 0 0 1 0 54 138 222 16 0 0 0 0 1 1 0 55 139 223 44 0 1 0 0 1 1 0 56 140 224 72 1 0 0 0 1 1 0 57 141 225 17 0 0 0 1 0 1 0 58 142 226 45 0 1 0 1 0 1 0 59 143 227 73 1 0 0 1 0 1 0 60 144 228 18 0 0 0 1 1 1 0 61 145 229 46 0 1 0 1 1 1 0 62 146 230 74 1 0 0 1 1 1 0 63 147 231 19 0 0 1 0 0 1 0 64 148 232 47 0 1 1 0 0 1 0 65 149 233 75 1 0 1 0 0 1 0 66 150 234 20 0 0 1 0 1 1 0 67 151 235 48 0 1 1 0 1 1 0 68 152 236 76 1 0 1 0 1 1 0 69 153 237 21 0 0 1 1 0 1 0 70 154 238 49 0 1 1 1 0 1 0 71 155 239 77 1 0 1 1 0 1 0 72 156 240 22 0 0 0 0 0 1 1 73 157 241 50 0 1 0 0 0 1 1 74 158 242 78 1 0 0 0 0 1 1 75 159 243 23 0 0 0 0 1 1 1 76 160 244 51 0 1 0 0 1 1 1 77 161 245 79 1 0 0 0 1 1 1 78 162 246 24 0 0 0 1 0 1 1 79 163 247 52 0 1 0 1 0 1 1 80 164 248 80 1 0 0 1 0 1 1 81 165 249 25 0 0 0 1 1 1 1 82 166 250 53 0 1 0 1 1 1 1 83 167 251 81 1 0 0 1 1 1 1 84 168 252 26 0 0 1 0 0 1 1 85 169 253 54 0 1 1 0 0 1 1 86 170 254 82 1 0 1 0 0 1 1 87 171 255 27 0 0 1 0 1 1 1 89 172 256 55 0 1 1 0 1 1 1 89 173 257 83 1 0 1 0 1 1 1 90 174 258 28 0 0 1 1 0 1 1 91 175 259 56 0 1 1 1 0 1 1 92 176 260 84 1 0 1 1 0 1 1 93 177 261 tug-3 a tug-3 b tug-3 c
- 89 of 154 - txc-04201b-mb ed. 4, september 2001 ds1mx7 txc-04201b data sheet proprietary transwitch corporation information for use solely by its customers auxiliary port the auxiliary port is used to access the j2, z6/n2, z7/k4 bytes, and the o-bit information, contained in the vt1.5 overhead. the auxiliary port consists of ten pins. the five output port pins are output port clock (oapcko), output port address valid (oapavo), output port address (oapado), output port data valid (oapdvo), and output port data (oapdto), all of which are output signals. the five input port pins are input port clock (iapcko, an output), input port address valid (iapavo, an output), input port address (iapado, an output), input port data valid (iapdvo, an output), input port data (iapdti, an input). figure 44 shows the auxiliary port operation. all signals are outputs except for iapdti, as noted above. input and output operations are identical. (o/i)apcko are continuous. an input or output transfer cycle requires 21 clock times. the cycle begins with (o/i)apavo transitioning high. input and output transfer cycles are asyn- chronous to each other. as indicated by the dotted lines, transfer cycles may overlap, i.e., address information can be output while data is being output or input. the minimum time between transfer cycles is one clock time. oapcko and iapcko are ? divide by 2 ? derivatives of dclk and aclk, respectively. data bytes are formatted with msb first. figure 44. auxiliary port operation input and output accesses require that telecom bus slots have been assigned to a specific channel; tbtval (bit 7) in control register x+05h and tbrval (bit 7) in control register x+04h are set to 1, and that the appro- priate control bits in register x+0bh for the overhead bytes are enabled. oapcko 8-bit data 12-bit address 0 1 2 3 4 5 6 7 8 9 10 11 1 2 3 4 5 6 7 8 iapcko oapado iapado oapavo iapavo oapdvo oapdto 8-bit data 1 2 3 4 5 6 7 8 iapdvo iapdti
- 90 of 154 - txc-04201b-mb ed. 4, september 2001 proprietary transwitch corporation information for use solely by its customers ds1mx7 txc-04201b data sheet the 12-bit address identifies the information that will be output or input during the transfer cycle. figure 45 details the address fields. the o-bits are output or input eight bits at a time (per vt super frame basis) where: 1. the first four o-bits (byte following j2, bits 3, 4, 5 and 6) are placed in bits 3, 2, 1 and 0 2. the second four o-bits (byte following z6/n2, bits 3, 4, 5 and 6) are placed in bits 7, 6, 5 and 4 figure 45. auxiliary port address designation the remaining bytes are mapped to the auxiliary port on a bit-for-bit basis. all five indicated bytes are output from information input on dd(0-7). in addition, the o-bits, j2, z6/n2, and z7/ k4 information will be written in the per channel memory map, for access by the microprocessor. register x+32h stores the received o-bits, x+33h is used to store the last received j2 byte, x+34h is used to store the last received z6/n2 byte and x+35h is used to store the last received z7/k4 byte. the input port will accept the o-bits, j2, z6/n2, and z7/k4 bytes. the v5 byte will not be requested. four per channel memory locations will be used for storage of outgoing o-bit, j2, z6/n2 and z7/k4 information. these locations will be available to the microprocessor to read the data collected by the auxiliary port. if an overhead byte is not to be input to the auxiliary port, these same memory locations can be used by the microprocessor to write a desired value which will be transmitted in the overhead byte location. control bit obapen (bit 3) in register x+0bh, when set to a 0, enables the o-bits for mapper channel n to be accessed from register x+36h and input to the correct position per figure 2 for inclusion in the vt1.5/ tu-11; when obapen is set to a 1, the o-bits for mapper channel n are requested at the auxiliary port input, written to the correct position per figure 2 for inclusion in the vt1.5/ tu-11, and also stored in register x+36h. control bit j2apen (bit 2) in register x+0bh, when set to a 0, enables the j2 byte for mapper channel n to be accessed from register x+37h and input to the correct position per figure 2 for inclusion in the vt1.5/ tu-11; when j2apen is set to a 1, the j2 byte for mapper channel n is requested at the auxiliary port input, written to the correct position per figure 2 for inclusion in the vt1.5/ tu-11, and also stored in register x+37h. control bit z6apen (bit 1) in register x+0bh, when set to a 0, enables the z6/n2 byte for mapper channel n to be accessed from register x+38h and input to the correct position per figure 2 for inclusion in the vt1.5/ tu-11; when z6apen is set to a 1, the z6/n2 byte for mapper channel n is requested at the auxiliary port input, written to the correct position per figure 2 for inclusion in the vt1.5/ tu-11, and also stored in register x+38h. control bit z7apen (bit 0) in register x+0bh, when set to a 0, enables the z7/k4 byte for mapper channel n to be accessed from register x+39h and input to the correct position per figure 2 for inclusion in the vt1.5/ tu-11; when z7apen is set to a 1, the z7/k4 byte for mapper channel n is requested at the auxiliary port input, written to the correct position per figure 2 for inclusion in the vt1.5/ tu-11, and also stored in register x+39h. it should be noted that bits 3, 2 and 1 of z7/ k4 are used for 3-bit rdi and will be overwritten with the appropriate values prior to transmission to the tele- com bus. a0 a11 0 vt1.5# 00=1 01=2 10=3 11=4 vtg# 000=1 001=2 010=3 011=4 sts-1# 00=1 01=2 10=3 11=not used overhead bits 0000 1010 1011=o-bits 1100=v5 100=5 101=6 110=7 1101=j2 1110=z6/n2 1111=z7/k4 not used 12-bit address 111=not used
- 91 of 154 - txc-04201b-mb ed. 4, september 2001 ds1mx7 txc-04201b data sheet proprietary transwitch corporation information for use solely by its customers ring port the ring port is used in ushr/p ring applications to communicate rei (febe) and rdi information between mated ds1mx7s. the ring port consists of six pins, three outputs and three inputs. the output port pins are output port clock (orpcko), output port frame (orpfmo), output port data (orpdto) and the input port pins are input port clock (irpcki), input port frame (irpfmi), input port data (irpdti). figure 46 shows the ring port operation and figure 49 shows an application. the information consists of seven eight-bit fields, one for each channel. the first four bits are rei-v (febe), rdi-vpd, rdi-vsd, and rdi-vcd. the last four bits are not used. the information is accumulated for all seven channels and sent as a burst of 56 bits. the orpcko is a ? divide by ten ? derivative of dclk. ring operation is enabled with the control bit ringen (bit 4) in register x+0bh. when set to zero, normal operations are performed. when set to one, ring mode is enabled. the information incoming on irpdti is stored in register x+3ah, bits 3-0 for access by the microprocessor. the designation for these bits is rgfebe-v (bit 3), rgrdi-vpd (bit 2), rgrdi-vsd (bit 1), and rgrdi-vcd (bit 0). the four remaining bits will be designated "unused". figure 46. ring port operation test access port introduction the ieee 1149.1 standard defines the requirements of a boundary scan architecture that has been specified by the ieee joint test action group (jtag). boundary scan is a specialized scan architecture that provides observability and controllability for the interface pins of the device. the test access port block, which imple- ments the boundary scan functions, consists of a test access port (tap) controller, instruction and test data registers, and a boundary scan register path bordering the input and output pins, as illustrated in figure 47. the boundary scan test bus interface consists of four input signals (i.e., the test clock (tck), test mode select (tms), test data input (tdi) and test reset (trs ) input signals) and a test data output (tdo) output signal. a brief description of boundary scan operation is provided below; further information is available in the ieee standard document. the tap controller receives external control information via a test clock (tck) signal, a test mode select (tms) signal, and a test reset (trs ) signal, and it sends control signals to the internal scan paths. the scan path architecture consists of a three-bit serial instruction register and two or more serial test data registers. the instruction and data registers are connected in parallel between the serial test data input (tdi) and test data output (tdo) signals. the test data input (tdi) signal is routed to both the instruction and test data reg- isters and is used to transfer serial data into a register during a scan operation. the test data output (tdo) is selected to send data from either register during a scan operation. channel 1 0 1 2 3 4 5 6 7 0 7 channel 7 0 1 2 3 4 5 6 7 0 1 rei-v rdi- rdi- rdi- vcd vsd vpd orpcko irpcki orpdto irpdti orpfmo irpfmi
- 92 of 154 - txc-04201b-mb ed. 4, september 2001 proprietary transwitch corporation information for use solely by its customers ds1mx7 txc-04201b data sheet when boundary scan testing is not being performed, the boundary scan register is transparent, allowing the input and output signals at the device pins to pass to and from the ds1mx7 device ? s internal logic, as illus- trated in figure 47. during boundary scan testing, the boundary scan register disables the normal flow of input and output signals to allow the device to be controlled and observed via scan operations. a timing diagram for the boundary scan feature is provided in figure 20. boundary scan support the maximum frequency the ds1mx7 device will support for boundary scan is 10 mhz. the ds1mx7 device performs the following boundary scan test instructions: - extest (000) - sample/preload (010) - bypass (111) it should be noted that the capture - ir state (instruction_capture attribute of bsdl) is 011. extest test instruction: one of the required boundary scan tests is the external boundary test (extest) instruction. when this instruction is shifted in, the ds1mx7 device is forced into an off-line test mode. while in this test mode, the test bus can shift data through the boundary scan registers to control the external ds1mx7 input and output leads. sample/preload test instruction: when the sample/preload instruction is shifted in, the ds1mx7 device remains fully operational. while in this test mode, ds1mx7 input data, and data destined for device outputs, can be captured and shifted out for inspection. the data is captured in response to control signals sent to the tap controller. bypass test instruction: when the bypass instruction is shifted in, the ds1mx7 device remains fully operational. while in this test mode, a scan operation will transfer serial data from the tdi input, through an internal scan cell, to the tdo pin. the purpose of this instruction is to abbreviate the scan path through the circuits that are not being tested to only a single clock delay.
- 93 of 154 - txc-04201b-mb ed. 4, september 2001 ds1mx7 txc-04201b data sheet proprietary transwitch corporation information for use solely by its customers boundary scan reset specific control of the trs lead is required in order to ensure that the boundary scan logic does not interfere with normal device operation. this lead must either be held low, asserted low, or asserted low then high (pulsed low), to asynchronously reset the test access port (tap) controller during power-up of the ds1mx7. if boundary scan testing is to be performed and the lead is held low, then a pull-down resistor value should be chosen which will allow the tester to drive this lead high, but still meet the v il requirements listed in the ? input, output and input/output parameters ? section of this data sheet for worst case leakage currents of all devices sharing this pull-down resistor. figure 47. boundary scan schematic tap controller test data registers instruction register tdi tdo in out boundary scan serial test data core logic of ds1mx7 boundary scan register signal input and output pins device trs tck tms control pins note: pin locations are shown for illustration only, and do not correspond to the physical device pins.
- 94 of 154 - txc-04201b-mb ed. 4, september 2001 proprietary transwitch corporation information for use solely by its customers ds1mx7 txc-04201b data sheet boundary scan chain there are 200 scan cells in the ds1mx7 boundary scan chain. bidirectional device pins require two scan cells. additional scan cells are used for direction control as needed. the following table shows the listed order of the scan cells and their functions. cells that are not associated with a pin are marked "na". scan cell number 0 is defined as the cell nearest the tdo pin and is therefore the first to be shifted out. the last scan cell to be shifted out is number 199. a boundary scan description language (bsdl) file for the ds1mx7 device is avail- able on the "products" page of the transwitch web site (www.transwitch.com). scan cell no. i/o pin no. symbol comments 199 input 196 irpdti 198 input 195 irpfmi 197 input 194 irpcki 196 output 193 orpdto 195 output 192 orpfmo 194 output 190 orpcko 193 output 189 lcs7 192 output 188 tsync7 191 output 187 ltclk7 190 output 186 tneg7 189 output 184 tpos7 188 control na den_7 a one makes pins 182 and 183 outputs. 187 bidir_in 183 rsync7 186 bidir_out 183 rsync7 185 bidir_in 182 lrclk7 184 bidir_out 182 lrclk7 183 control na rneg7_en a one makes pin 180 an output. 182 bidir_in 180 rneg7 181 bidir_out 180 rneg7 180 input 178 rpos7 179 input 177 lais7 178 output 176 lcs6 177 output 175 tsync6 176 output 174 ltclk6 175 output 172 tneg6 174 output 171 tpos6 173 control na den_6 a one makes pins 168 and 170 outputs. 172 bidir_in 170 rsync6 171 bidir_out 170 rsync6 170 bidir_in 168 lrclk6 169 bidir_out 168 lrclk6 168 control na rneg6_en a one makes pin 166 an output.
- 95 of 154 - txc-04201b-mb ed. 4, september 2001 ds1mx7 txc-04201b data sheet proprietary transwitch corporation information for use solely by its customers 167 bidir_in 166 rneg6 166 bidir_out 166 rneg6 165 input 165 rpos6 164 input 164 lais6 163 output 163 lcs5 162 output 162 tsync5 161 output 160 ltclk5 160 output 159 tneg5 159 output 158 tpos5 158 control na den_5 a one makes pins 156 and 157 outputs. 157 bidir_in 157 rsync5 156 bidir_out 157 rsync5 155 bidir_in 156 lrclk5 154 bidir_out 156 lrclk5 153 control na rneg5_en a one makes pin 155 an output. 152 bidir_in 155 rneg5 151 bidir_out 155 rneg5 150 input 154 rpos5 149 input 152 lais5 148 output 150 lcs4 147 output 149 tsync4 146 output 148 ltclk4 145 output 147 tneg4 144 output 146 tpos4 143 control na den_4 a one makes pins 143 and 144 outputs. 142 bidir_in 144 rsync4 141 bidir_out 144 rsync4 140 bidir_in 143 lrclk4 139 bidir_out 143 lrclk4 138 control na rneg4_out a one makes pin 142 an output. 137 bidir_in 142 rneg4 136 bidir_out 142 rneg4 135 input 140 rpos4 134 input 138 lais4 133 output 137 lcs3 132 output 136 tsync3 131 output 135 ltclk3 130 output 134 tneg3 scan cell no. i/o pin no. symbol comments
- 96 of 154 - txc-04201b-mb ed. 4, september 2001 proprietary transwitch corporation information for use solely by its customers ds1mx7 txc-04201b data sheet 129 output 132 tpos3 128 control na den_3 a one makes pins 130 and 131 outputs. 127 bidir_in 131 rsync3 126 bidir_out 131 rsync3 125 bidir_in 130 lrclk3 124 bidir_out 130 lrclk3 123 control na rneg3_en a one makes pin 128 an output. 122 bidir_in 128 rneg3 121 bidir_out 128 rneg3 120 input 126 rpos3 119 input 125 lais3 118 output 124 lcs2 117 output 123 tsync2 116 output 122 ltclk2 115 output 120 tneg2 114 output 119 tpos2 113 control na den_2 a one makes pins 116 and 118 outputs. 112 bidir_out 118 rsync2 111 bidir_in 118 rsync2 110 bidir_out 116 lrclk2 109 bidir_in 116 lrclk2 108 control na rneg2_en a one makes pin 114 an output. 107 bidir_in 114 rneg2 106 bidir_out 114 rneg2 105 input 113 rpos2 104 input 112 lais2 103 output 111 lcs1 102 output 110 tsync1 101 output 108 ltclk1 100 output 107 tneg1 99 output 106 tpos1 98 control na den_1 a one makes pins 104 and 105 outputs. 97 bidir_in 105 rsync1 96 bidir_out 105 rsync1 95 bidir_in 104 lrclk1 94 bidir_out 104 lrclk1 93 control na rneg1_en a one makes pin 103 an output. 92 bidir_in 103 rneg1 scan cell no. i/o pin no. symbol comments
- 97 of 154 - txc-04201b-mb ed. 4, september 2001 ds1mx7 txc-04201b data sheet proprietary transwitch corporation information for use solely by its customers 91 bidir_out 103 rneg1 90 input 102 rpos1 89 input 100 lais1 88 input 98 lo 87 input 97 master 86 input 96 daten 85 input 95 configi 84 output 94 lsclk 83 input 92 lsdi 82 output 91 lsdo 81 input 90 buschk2 80 input 89 buschk1 79 input 88 buschk0 78 control na data_en_drive a one enables output1. 77 output1 86 ad0 76 output1 85 ad1 75 output1 84 ad2 74 output1 83 ad3 73 output1 82 ad4 72 output1 80 ad5 71 output1 79 ad6 70 output1 78 ad7 69 input 76 aclk 68 output 74 aadd 67 input 72 ac1j1v1 66 input 71 aspe 65 output1 70 apar 64 input 68 dfail 63 input 67 dspe 62 input 66 dc1j1v1 61 input 64 dclk 60 input 62 dpar 59 input 61 dd0 58 input 60 dd1 57 input 59 dd2 56 input 58 dd3 55 input 56 dd4 54 input 55 dd5 scan cell no. i/o pin no. symbol comments
- 98 of 154 - txc-04201b-mb ed. 4, september 2001 proprietary transwitch corporation information for use solely by its customers ds1mx7 txc-04201b data sheet 53 input 54 dd6 52 input 53 dd7 51 output 52 oapdvo 50 output 51 oapdto 49 output 50 oapavo 48 output 49 iapcko 47 output 48 oapado 46 output 46 iapdvo 45 input 45 iapdti 44 output 44 iapavo 43 output 43 iapado 42 output 42 oapcko 41 output 40 pcki 40 input 39 wri 39 input 38 motoi 38 input 36 seli 37 input 34 readi / readi/wri 36 output 32 into 35 control na rdy_en a one enables pin 31; a zero tristates pin 31. 34 output2 31 rdyo 33 control na data_en a one makes pins 19 through 30 outputs. 32 bidir_in 30 dtb7 31 bidir_out 30 dtb7 30 bdir_in 28 dtb6 29 bidir_out 28 dtb6 28 bidir_in 26 dtb5 27 bidir_out 26 dtb5 26 bdir_in 24 dtb4 25 bidir_out 24 dtb4 24 bidir_in 22 dtb3 23 bidir_out 22 dtb3 22 bdir_in 21 dtb2 21 bidir_out 21 dtb2 20 bidir_in 20 dtb1 19 bidir_out 20 dtb1 18 bdir_in 19 dtb0 17 bidir_out 19 dtb0 16 input 18 addr8 scan cell no. i/o pin no. symbol comments
- 99 of 154 - txc-04201b-mb ed. 4, september 2001 ds1mx7 txc-04201b data sheet proprietary transwitch corporation information for use solely by its customers device reset procedure after power-up the ds1mx7 requires a hardware reset. this reset will reset all the per channel registers in the memory map. it will also reset all of the global registers at addresses 04h through 03fh. a low placed on the rsti lead for at least 10 cycles of pcki after all clocks become stable will accomplish the hardware reset. a global software reset is also available and should be applied at least 10 ms after power-up. this resets the internal state machines. it does not change the state of any of the control registers, performance counters and latched shadow registers. writing a 91h to control byte reset in register 005h places the ds1mx7 in a reset state. writing a value other than 91h to control byte reset will take the ds1mx7 out of the reset state. the reset register can be read to determine the reset state of the ds1mx7. a value of 01h in the reset register indicates the ds1mx7 is in a reset state; a value of 00h indicates the ds1mx7 is not in reset. a per channel version of this function is available by writing a 1 to control bit rstch (bit 5) in register x0ch followed by writ- ing a 0 to control bit rstch. changing the mode of operation of a mapper should be followed by a per channel software reset (rstch). the mode bits can be found in mapper per channel registers x+00h through x+02h (explos, datacom, enzc, lcode, encod, mode1, mode0 and crc6). not resetting the mapper after changing other mode control bits will have minimal effect. if all 7 channels of the ds1mx7 are not implemented in an application, the channels that are not used should be powered down (control bit idle, bit 7 in register x+00h is set to a 0) and all interrupts masked (registers x+09h through x+0bh set to ffh). 15 input 16 addr7 14 input 15 addr6 13 input 14 addr5 12 input 12 addr4 11 input 10 addr3 10 input 9 addr2 9 input 8 addr1 8 input 7 addr0 7 input 6 cso 6 input 4 rsti 5 input 3 highz 4 input 2 tstb 3 input 1 tsta 2output208 iao 1 input 207 t1si 0 input 206 srclk scan cell no. i/o pin no. symbol comments
- 100 of 154 - txc-04201b-mb ed. 4, september 2001 proprietary transwitch corporation information for use solely by its customers ds1mx7 txc-04201b data sheet memory map common memory map hex address range channel functions 000 - 03f common component id. serial port control, global control, device controls and interrupt control 040 - 07f #1 status, control, pm/fm and error counters 080 - 0bf #2 status, control, pm/fm and error counters 0c0 - 0ff #3 status, control, pm/fm and error counters 100 - 13f #4 status, control, pm/fm and error counters 140 - 17f #5 status, control, pm/fm and error counters 180 - 1bf #6 status, control, pm/fm and error counters 1c0 - 1ff #7 status, control, pm/fm and error counters address (hex) mode* bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 000 r mi7=1 mi6=1 mi5=0 mi4=1 mi3=0 mi2=1 mi1=1 mi0=1 001 r pn3=1 pn2=0 pn1=0 pn0=1 mi11=0 mi10=0 mi9=0 mi8=0 002 r pn11=0 pn10=0 pn9=0 pn8=0 pn7=0 pn6=1 pn5=1 pn4=0 003 r v3=0 v2=0 v1=1 v0=0 pn15=0 pn14=0 pn13=0 pn12=1 004 r/w notebook 005 r/w reset 006 r/w gim rise fall ipol enpmfm enhwm r r 007 r/w tcae rcae sdh rxnrzp tbpis tbpe vc3vc4 txnrzp 008 r/w mtbrcf mtbrsf mtbrpf r mmckf mtbtcf mtbtsf mtbtpf 009 r/w r r r r mtbrpy mprbse mtbie mtbxe 00a r tbrcks tbrsns tbrpas r mcks tbtcks tbtsns tbtpas 00b r r r r r tbrpys prbss tbies tbxes 00c r/w=clr tbrcke tbrsne tbrpae r mcke tbtcke tbtsne tbtpae 00d r/w=clr r r r r tbrpye prbse tbiee tbxee 00e r/w=clr tbrckpm tbrsnpm tbrpapm r mckpm tbtckpm tbtsnpm tbtpapm 00f r/w=clr r r r r tbrpypm prbspm tbiepm tbxepm 010 - spare 011 r r ch7 ch6 ch5 ch4 ch3 ch2 ch1 012 - spare notes: *r/w: read/write; r: read-only; w: write-only; r/w=clr: read/write zero bits only (one bits ignored during write). bits shown as 'r' and bytes shown as 'reserved' must be set to 0/00h for proper device operation, where write capability is pro vided. spare registers must not be accessed by the microprocessor.
- 101 of 154 - txc-04201b-mb ed. 4, september 2001 ds1mx7 txc-04201b data sheet proprietary transwitch corporation information for use solely by its customers per channel memory map note: in the address, x= 040h for ds1 channel 1; 080h for ds1 channel 2; 0c0h for ds1 channel 3; 100h for ds1 channel 4; 140h f or ds1 channel 5; 180h for ds1 channel 6; 1c0h for ds1 channel 7. 013 r gxpe gdmpe glose gmpe gdaise grpoe gpgoe gcvoe 014 r gfeoe gbipoe gvaise glope grfie gunee gslme grdie 015 r/w gxpm gdmpm glosm gmpm gdaism grpom gpgom gcvom 016 r/w gfeom gbipom gvaism glopm grfim gunem gslmm grdim 017 r/w d7 d6 d5 d4 d3 d2 d1 d0 018 r/w d7 d6 d5 d4 d3 d2 d1 d0 019 r d7 d6 d5 d4 d3 d2 d1 d0 01a r/w bdcst r eprbsa ensrp r ds1 channel number (0-6) 01b r/w etbrcf etbrsf etbrpf r emckf etbtcf etbtsf etbtpf 01c r/w r r r r etbrpy eprbse etbie etbxe 01d r/w ectl7 ectl6 ectl5 ectl4 ectl3 ectl2 ectl1 ectl0 01e r/w tblpbk ftbtpe tbtci tbrci tbdd r r rdid10 01f - 03b - spare 03c r/w dplllk dpll6 dpll5 dpll4 dpll3 dpll2 dpll1 dpll0 03d r/w r r r byplb prbsck tmdis c2ph1 c2ph0 03e r/w=clr tbrckfm tbrsnfm tbrpafm r mckfm tbtckfm tbtsnfm tbtpafm 03f r/w=clr r r r r tbrpyfm prbsfm tbiefm tbxefm address (hex) mode bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 x+00 r/w idle explos datacom enzc lcode encod mode1 mode0 x+01 r/w sh2vais los2ais lof2vais crc6 vais2ais rfi2yel yel2rfi ais2vais x+02 r/w srdi-vpd srdi-vsd srdi-vcd r rdiis slm2ais febeis une2ais x+03 r/w sfebe sdaiss sbipe r sdaisl syell srfi svtais x+04 r/w tbrval tel bus rx sts-1 number (1-3) tel bus rx vt group or tug number (1-7) tel bus rx vt or tu number (1-4) x+05 r/w tbtval tel bus tx sts-1 number (1-3) tel bus tx vt group or tug number (1-7) tel bus tx vt or tu number (1-4) x+06 r/w pl8 pl7 pl6 pl5 pl4 pl3 pl2 pl1 x+07 r/w r expected signal label (2-0) r transmit signal label (2-0) x+08 r/w xpm dmpm losm mpm daism rpom pgom cvom x+09 r/w feom bipom vaism lopm rfim unem slmm rdim x+0ar/wr r rrr rdi-vpdm rdi-vsdm rdi-vcdm address (hex) mode* bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0
- 102 of 154 - txc-04201b-mb ed. 4, september 2001 proprietary transwitch corporation information for use solely by its customers ds1mx7 txc-04201b data sheet x+0b r/w r r r ringen obapen j2apen z6apen z7apen x+0c r/w dtlpbk dflpbk rstch sprbs r r r r x+0d - x+0f - reserved x+10 r xps dmps loss mps daiss rpos pgos cvos x+11 r feos bipos vaiss lops rfis unes slms rdi-vs x+12 r r r r r r rdi-vpds rdi-vsds rdi-vcds x+13 - spare x+14 r/w=clr xpe dmpe lose mpe daise rpoe pgoe cvoe x+15 r/w=clr feoe bipoe vaise lope rfie unee slme rdi-ve x+16 r/w=clr r r r r r rdi-vpde rdi-vsde rdi-vcde x+17 - spare x+18 r/w=clr xppm dmppm lospm mppm daispm rpopm pgopm cvopm x+19 r/w=clr feopm bipopm vaispm loppm rfipm unepm slmpm rdi-vpm x+1a r/w=clr r r r r r rdi-vpdpm rdi-vsdpm rdi-vcdpm x+1b - spare x+1c r/w=clr xpfm dmpfm losfm mpfm daisfm rpofm pgofm cvofm x+1d r/w=clr feofm bipofm vaisfm lopfm rfifm unefm slmfm rdi-vfm x+1e r/w=clr r r r r r rdi-vpdfm rdi-vsdfm rdi-vcdfm x+1f - spare x+20 r shdais shyel r rxss1 rxss0 received signal label (2-0) x+21 - spare x+22 r/w=clr cvc7 cvc6 cvc5 cvc4 cvc3 cvc2 cvc1 cvc0 x+23 r/w=clr r r r r cvc11 cvc10 cvc9 cvc8 x+24 r/w=clr count of pointer increments received count of pointer decrements received x+25 r/w=clr count of pointer increments generated count of pointer decrements generated x+26 r/w=clr bec7 bec6 bec5 bec4 bec3 bec2 bec1 bec0 x+27 r/w=clr r r r r bec11 bec10 bec9 bec8 x+28 r/w=clr fec7 fec6 fec5 fec4 fec3 fec2 fec1 fec0 x+29 r/w=clr r r r r fec11 fec10 fec9 fec8 x+2a r/w lcvc7 lcvc6 lcvc5 lcvc4 lcvc3 lcvc2 lcvc1 lcvc0 x+2b r/w r r r r lcvc11 lcvc10 lcvc9 lcvc8 x+2c r/w latched count of pointer increments received latched count of pointer decrements received x+2d r/w latched count of pointer increments generated latched count of pointer decrements generated x+2e r/w lbec7 lbec6 lbec5 lbec4 lbec3 lbec2 lbec1 lbec0 address (hex) mode bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0
- 103 of 154 - txc-04201b-mb ed. 4, september 2001 ds1mx7 txc-04201b data sheet proprietary transwitch corporation information for use solely by its customers x+2f r/w r r r r lbec11 lbec10 lbec9 lbec8 x+30 r/w lfec7 lfec6 lfec5 lfec4 lfec3 lfec2 lfce1 lfec0 x+31 r/w r r r r lfec11 lfec10 lfec9 lfec8 x+32 r rx o-bits x+33 r rx j2 x+34 r rx z6/n2 x+35 r rx z7/k4 x+36 r/w tx o-bits x+37 r/w tx j2 x+38 r/w tx z6/n2 x+39 r/w tx z7/k4 x+3a r r r r r rgfebe-v rgrdi-vpd rgrdi-vsd rgrdi-vcd x+3b - x+3f reserved address (hex) mode bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0
- 104 of 154 - txc-04201b-mb ed. 4, september 2001 proprietary transwitch corporation information for use solely by its customers ds1mx7 txc-04201b data sheet memory map descriptions common memory map component id global registers address bit symbol description 000 7-0 mi7-mi0 manufacturer identity: read-only register containing the seven least significant bits of the component manufacturer ? s identity (107 decimal) followed by a 1 in bit 0 (d7 hex). 001 7-4 pn3-pn0 part number: read-only register containing the four least significant bits of the component part number (9 hex). 3-0 mi11-mi8 manufacturer identity: read-only register containing the four most sig- nificant bits of the component manufacturer ? s identity (0 hex). 002 7-0 pn11-pn4 part number: read-only register containing the middle eight bits of the component part number (06 hex). 003 7-4 v3-v0 version: read-only register containing the component version number (2 hex). 3-0 pn15-pn12 part number: read-only register containing the four most significant bits of the component part number (1 hex). 004 7-0 notebook user register: read/write register for end-user application. the content of this register will have no effect on the operation of the device. 005 7-0 reset software reset: writing a 91 hex into this location will generate a soft- ware reset to the component (all but configuration registers are reset). writing other than 91 hex will remove the ds1mx7 from the reset state. reading this location will return a 00 hex if the ds1mx7 is not in reset and 01 hex if the ds1mx7 is in reset. the ds1mx7 will default to reset on application of external hardware reset (rsti ). address bit symbol description 006 7 gim global interrupt mask: when cleared (this bit set to zero), the external interrupt output (into/irqo , pin 32) will be asserted when an internal interrupt event occurs. the internal interrupt status may still be polled by software to detect interrupt events when this bit is set to one. 6rise rising edge interrupt: when set to one, a status change will be regis- tered as a one in the latched value bits on the start of an event. 5fall falling edge interrupt: when set to one, a status change will be regis- tered as a one in the latched value bits on the end of an event. 4ipol interrupt polarity: when set to one, the polarity of the interrupt pin will be inverted at the pin.
- 105 of 154 - txc-04201b-mb ed. 4, september 2001 ds1mx7 txc-04201b data sheet proprietary transwitch corporation information for use solely by its customers 006 (cont.) 3enpmfm enable pm/fm function: when set to one, the performance and fault monitoring function is in the pm/fm registers (00e/f, 03e/f, x+18h to x+1eh) and the latched counters (x+2ah to x+31h); latching takes place after t1si rising edge. both rise and fall must be set to one. 2 enhwm enable hardware mask: when set to one, global errors (e.g., dclk fails; tbrcks = 1) may be used to generate an active low internal alarm output on pin iao , if enabled (e.g., control bit etbrcf = 1). when set to zero, pin iao will remain high. 1-0 r reserved: these bits must be set to zero. 007 7 tcae tributary transmit clock active edge: if this bit is set to one, the tposn, tnegn/tsigln and tsyncn signals are clocked out of the ds1mx7 on the rising edge of ltclkn. when set to zero, they are clocked out on the falling edge of ltclkn. 6 rcae tributary receive clock active edge: if this bit is set to one, the rposn, rnegn/rsigln/rcvn and rsyncn signals are clocked into the ds1mx7 on the rising edge of lrclkn and out of the ds1mx7 on the falling edge of lrclkn. when set to zero, they are clocked in or out on the falling/rising edge of lrclkn respectively. 5sdh sdh functions: when this bit is set to one, the pointer tracking state machine will transition from the ais state to the lop state on receipt of eight invalid pointers and a block count of bip-2 errors will be recorded by the bip-2 error counter. this is used in sdh applications. when set to zero, the pointer tracking state machine will not include the ais state to the lop state transition and the actual number of bip-2 errors will be recorded by the bip-2 error counter. this setting is used in sonet appli- cations. 4 rxnrzp receive nrz polarity: when set to one, the polarity of the data received at rposn and laisn will be inverted at these pins; a low will be interpreted as a logic one. 3tbpis telecom bus parity includes sync.: when set to one, the signals ac1j1v1 and aspe are included with ad(0-7) in the parity calculation for apar. when set to zero, apar includes parity calculated for ad(0-7) only. 2 tbpe telecom bus parity even/odd: when set to one, even parity is calcu- lated for apar and checked for dpar. when set to zero, odd parity is calculated for apar and checked for dpar. 1vc3vc4 vc3 / vc4 telecom bus operation: when set to one, the telecom bus operates with stuffing per sonet requirements and sdh requirements for a tu-11 in a tug-2, vc-3, au-3 at either 6.48 or 19.44 mhz. when set to zero, the telecom bus operates with stuffing per sdh require- ments for a tu-11 in a tug-2 via a tug-3, vc-3, au-4 at 19.44 mhz only. pin configi must be set to low if sdh stuffing is required. 0 txnrzp transmit nrz polarity: when set to one, the polarity of the data trans- mitted at tposn will be inverted at the pin; a logic one will generate a low output signal. address bit symbol description
- 106 of 154 - txc-04201b-mb ed. 4, september 2001 proprietary transwitch corporation information for use solely by its customers ds1mx7 txc-04201b data sheet 008 7 mtbrcf mask telecom bus receive clock fail: when set to one, the fault detector for dclk is masked from generating an interrupt (status and event not affected). 6mtbrsf mask telecom bus receive sync. fail: when set to one, the fault detector for dc1j1v1 is masked from generating an interrupt (status and event not affected). 5mtbrpf mask telecom bus receive payload indicator fail: when set to one, the fault detector for dspe is masked from generating an interrupt (sta- tus and event not affected). 4r reserved: this bit must be set to zero. 3 mmckf mask master clock fail: when set to one, the fault detector for srclk is masked from generating an interrupt (status and event not affected). 2 mtbtcf mask telecom bus transmit clock fail: when set to one, the fault detector for aclk is masked from generating an interrupt (status and event not affected). 1mtbtsf mask telecom bus transmit sync. fail: when set to one, the fault detector for ac1j1v1 is masked from generating an interrupt (status and event not affected). 0mtbtpf mask telecom bus transmit payload indicator fail: when set to one, the fault detector for aspe is masked from generating an interrupt (sta- tus and event not affected). 009 7-4 r reserved: these bits must be set to zeros. 3mtbrpy mask telecom bus receive parity error: when set to one, the parity error detector for the received telecom bus is masked from generating an interrupt (status and event not affected). 2mprbse mask prbs out of lock events: when set to one, the prbs analyzer out of lock output is masked from generating an interrupt (status and event not affected). 1mtbie mask telecom bus internal error: when set to one, the fault detector for telecom bus transmit internal collisions is masked from generating an interrupt (status and event not affected). 0mtbxe mask telecom bus external error: when set to one, the fault detector for telecom bus transmit external collisions is masked from generating an interrupt (status and event not affected). address bit symbol description
- 107 of 154 - txc-04201b-mb ed. 4, september 2001 ds1mx7 txc-04201b data sheet proprietary transwitch corporation information for use solely by its customers 00a 7 tbrcks telecom bus receive clock fail status: when set to one, the fault detector for dclk is currently detecting loss of transitions. this bit is set to a 1 when no dclk transitions are detected for a time between 32 and 64 cycles of pcki. this bit is cleared to 0 when dclk transitions are present for between 32 and 64 cycles of pcki. 6 tbrsns telecom bus receive sync. fail status: when set to one, the fault detector for dc1j1v1 is currently detecting loss of transitions. detection time is 2000 500 microseconds; clear time is a single transition of dc1j1v1. 5tbrpas telecom bus receive payload indicator fail status: when set to one, the fault detector for dspe is currently detecting loss of transitions. mini- mum detection time is 35 microseconds; clear time is a single transition of dspe. 4r reserved: this bit reads out as zero. 3mcks master clock fail status: when set to one, the fault detector for srclk is currently detecting loss of transitions. detection time is 2.0 0.5 microseconds (32 cycles of pcki @ 16 mhz); this bit is cleared to zero when srclk is present for 32 cycles of pcki. 2tbtcks telecom bus transmit clock fail status: when set to one, the fault detector for aclk is currently detecting loss of transitions. this bit is set to a 1 when no aclk transitions are detected for a time between 32 and 64 cycles of pcki. this bit is cleared to 0 when aclk transitions are present for between 32 and 64 cycles of pcki. 1tbtsns telecom bus transmit sync. fail status: when set to one, the fault detector for ac1j1v1 is currently detecting loss of transitions. detection time is 2000 500 microseconds; clear time is a single transition of ac1j1v1. 0tbtpas telecom bus transmit payload indicator fail status: when set to one, the fault detector for aspe is currently detecting loss of transitions. minimum detection time is 49 microseconds; clear time is a single transi- tion of aspe. 00b 7-4 r reserved: these bits read out as zeros. 3tbrpys telecom bus receive parity error status: when set to one, the parity error detector for the received telecom bus is detecting a parity error. 2prbss prbs out of lock status: when set to one, the prbs analyzer is out of lock. 1 tbies telecom bus internal error status: when set to one, the fault detector for telecom bus transmit internal collisions is detecting simultaneous bus slot access (i.e., two or more channel registers at x+05h set to same slot). 0 tbxes telecom bus external error status: when set to one, the fault detector for telecom bus transmit external collisions is detecting simultaneous bus slot access as determined by the aadd and buschk pin levels. address bit symbol description
- 108 of 154 - txc-04201b-mb ed. 4, september 2001 proprietary transwitch corporation information for use solely by its customers ds1mx7 txc-04201b data sheet 00c 7 tbrcke telecom bus receive clock fail latched event: this bit will be set to one when the active edge, as selected by rise and fall, has occurred for dclk loss of clock. if not masked, an interrupt and/or internal alarm is generated when this bit is set. this bit is cleared only by writing it to zero. 6 tbrsne telecom bus receive sync. fail latched event: this bit will be set to one when the active edge, as selected by rise and fall, has occurred for dc1j1v1 loss of signal. if not masked, an interrupt and/or internal alarm is generated when this bit is set. this bit is cleared only by writing it to zero. 5tbrpae telecom bus receive payload indicator fail latched event: this bit will be set to one when the active edge, as selected by rise and fall, has occurred for dspe loss of signal. if not masked, an interrupt and/or internal alarm is generated when this bit is set. this bit is cleared only by writing it to zero. 4r reserved: this bit must be set to zero. 3mcke master clock fail latched event: this bit will be set to one when the active edge, as selected by rise and fall, has occurred for srclk loss of clock. if not masked, an interrupt and/or internal alarm is gener- ated when this bit is set. this bit is cleared only by writing it to zero. 2tbtcke telecom bus transmit clock fail latched event: this bit will be set to one when the active edge, as selected by rise and fall, has occurred for aclk loss of clock. if not masked, an interrupt and/or internal alarm is generated when this bit is set. this bit is cleared only by writing it to zero. 1tbtsne telecom bus transmit sync. fail latched event: this bit will be set to one when the active edge, as selected by rise and fall, has occurred for ac1j1v1 loss of signal. if not masked, an interrupt and/or internal alarm is generated when this bit is set. this bit is cleared only by writing it to zero. 0tbtpae telecom bus transmit payload indicator fail latched event: this bit will be set to one when the active edge, as selected by rise and fall, has occurred for aspe loss of signal. if not masked, an interrupt and/or internal alarm is generated when this bit is set. this bit is cleared only by writing it to zero. address bit symbol description
- 109 of 154 - txc-04201b-mb ed. 4, september 2001 ds1mx7 txc-04201b data sheet proprietary transwitch corporation information for use solely by its customers 00d 7-4 r reserved: these bits must be set to zeros. 3tbrpye telecom bus receive parity error latched event: this bit will be set to one when the active edge, as selected by rise and fall, has occurred for a parity error. if not masked, an interrupt and/or internal alarm is generated when this bit is set. this bit is cleared only by writing it to zero. 2prbse prbs out of lock latched event: this bit will be set to one when the active edge, as selected by rise and fall, has occurred for a prbs out of lock condition. if not masked, an interrupt and/or internal alarm is gen- erated when this bit is set. this bit is cleared only by writing it to zero. 1 tbiee telecom bus internal error latched event: this bit will be set to one when the active edge, as selected by rise and fall, has occurred for an internal bus error. if not masked, an interrupt and/or internal alarm is generated when this bit is set. this bit is cleared only by writing it to zero. 0 tbxee telecom bus external error latched event: this bit will be set to one when the active edge, as selected by rise and fall, has occurred for an external bus error. if not masked, an interrupt and/or internal alarm is generated when this bit is set. this bit is cleared only by writing it to zero. 00e 7 tbrckpm telecom bus receive clock performance monitor: this bit will be set to one if dclk loss of clock has occurred at any time in the last one-sec- ond interval as defined by t1si. this bit is cleared by writing it to zero or by t1si rising edge if the condition no longer exists and event bit tbrcke has been cleared. 6 tbrsnpm telecom bus receive sync. performance monitor: this bit will be set to one if dc1j1v1 loss of signal has occurred at any time in the last one- second interval as defined by t1si. this bit is cleared by writing it to zero or by t1si rising edge if the condition no longer exists and event bit tbrsne has been cleared. 5 tbrpapm telecom bus receive payload indicator performance monitor: this bit will be set to one if dspe loss of signal has occurred at any time in the last one-second interval as defined by t1si. this bit is cleared by writing it to zero or by t1si rising edge if the condition no longer exists and event bit tbrpae has been cleared. 4r reserved: this bit must be set to zero. 3mckpm master clock performance monitor: this bit will be set to one if srclk loss of clock has occurred at any time in the last one-second interval as defined by t1si. this bit is cleared by writing it to zero or by t1si rising edge if the condition no longer exists and event bit mcke has been cleared. 2 tbtckpm telecom bus transmit clock performance monitor: this bit will be set to one if aclk loss of clock has occurred at any time in the last one- second interval as defined by t1si. this bit is cleared by writing it to zero or by t1si rising edge if the condition no longer exists and event bit tbtcke has been cleared. address bit symbol description
- 110 of 154 - txc-04201b-mb ed. 4, september 2001 proprietary transwitch corporation information for use solely by its customers ds1mx7 txc-04201b data sheet 00e (cont.) 1 tbtsnpm telecom bus transmit sync. performance monitor: this bit will be set to one if ac1j1v1 loss of signal has occurred at any time in the last one- second interval as defined by t1si. this bit is cleared by writing it to zero or by t1si rising edge if the condition no longer exists and event bit tbtsne has been cleared. 0 tbtpapm telecom bus transmit payload indicator performance monitor: this bit will be set to one if aspe loss of clock has occurred at any time in the last one-second interval as defined by t1si. this bit is cleared by writing it to zero or by t1si rising edge if the condition no longer exists and event bit tbtpae has been cleared. 00f 7-4 r reserved: these bits must be set to zeros. 3 tbrpypm telecom bus receive parity error performance monitor: this bit will be set to one if a parity error has occurred at any time in the last one-sec- ond interval as defined by t1si. this bit is cleared by writing it to zero or by t1si rising edge if the condition no longer exists and event bit tbrpye has been cleared. 2prbspm prbs out of lock performance monitor: this bit will be set to one if a prbs out of lock has occurred at any time in the last one-second interval as defined by t1si. this bit is cleared by writing it to zero or by t1si ris- ing edge if the condition no longer exists and event bit prbse has been cleared. 1tbiepm telecom bus internal error performance monitor: this bit will be set to one if an internal bus collision has occurred at any time in the last one- second interval as defined by t1si. this bit is cleared by writing it to zero or by t1si rising edge if the condition no longer exists and event bit tbxie has been cleared. 0 tbxepm telecom bus external error performance monitor: this bit will be set to one if an external bus collision has occurred at any time in the last one-second interval as defined by t1si. this bit is cleared by writing it to zero or by t1si rising edge if the condition no longer exists and event bit tbxee has been cleared. 010 7-0 spare spare: this register should not be accessed. 011 7 r reserved: this bit reads out as zero. 6-0 ch7 - ch1 channel activity: a bit is set to one for any channel that has one or more pending events. it is used as a polling register to identify channels in need of service or to locate channels that have generated an interrupt. 012 7-0 spare spare: this register should not be accessed. address bit symbol description
- 111 of 154 - txc-04201b-mb ed. 4, september 2001 ds1mx7 txc-04201b data sheet proprietary transwitch corporation information for use solely by its customers 013 7 gxpe global external lais pin event: this bit will be set to one if an active signal is present (xpe is one) in any of the channels for lais. this bit will be cleared when all lais events have been cleared in the individual channel event registers. 6gdmpe global demap error event: this bit will be set to one if a demap error event (dmpe) is present in any of the channels. this bit will be cleared when all demap error events have been cleared in the individual channel event registers. 5glose global los event: this bit will be set to one if a ds1 loss of signal event (lose) is present in any of the channels. this bit will be cleared when all ds1 loss of signal events have been cleared in the individual channel event registers. 4gmpe global map error event: this bit will be set to one if a map error event (mpe) is present in any of the channels. this bit will be cleared when all map error events have been cleared in the individual channel event reg- isters. 3gdaise global ds1 ais event: this bit will be set to one if a ds1 ais event (daise) is present in any of the channels. this bit will be cleared when all ds1 ais events have been cleared in the individual channel event registers. 2grpoe global received pointer justification counter overflow event: this bit will be set to one if a received pointer justification counter overflow event (rpoe) is present in any of the channels. this bit will be cleared when all receive pointer counter overflow events have been cleared in the individual channel event registers. 1 gpgoe global generated pointer justification counter overflow event: this bit will be set to one if a generated pointer justification counter over- flow event (pgoe) is present in any of the channels. this bit will be cleared when all pointer generation counter overflow events have been cleared in the individual channel event registers. 0gcvoe global code violation counter/crc-6 error counter overflow event: this bit will be set to one if a code violation counter/crc-6 error counter overflow event (cvoe) is present in any of the channels. this bit will be cleared when all code violation counter/crc-6 error counter over- flow events have been cleared in the individual channel event registers. address bit symbol description
- 112 of 154 - txc-04201b-mb ed. 4, september 2001 proprietary transwitch corporation information for use solely by its customers ds1mx7 txc-04201b data sheet 014 7 gfeoe global rei (febe) counter overflow event: this bit will be set to one if a rei (febe) counter overflow event (feoe) is present in any of the channels. this bit will be cleared when all rei (febe) counter overflow events have been cleared in the individual channel event registers. 6 gbipoe global bip-2 error counter overflow event: this bit will be set to one if a bip-2 error counter overflow event (bipoe) is present in any of the channels. this bit will be cleared when all bip-2 error counter overflow events have been cleared in the individual channel event registers. 5gvaise global vt ais event: this bit will be set to one if a vt ais event (vaise) is present in any of the channels. this bit will be cleared when all vt ais events have been cleared in the individual channel event reg- isters. 4glope global loss of pointer event: this bit will be set to one if a loss of pointer event (lope) is present in any of the channels. this bit will be cleared when all loss of pointer events have been cleared in the individ- ual channel event registers. 3grfie global rfi event: this bit will be set to one if a remote failure indication event (rfie) is present in any of the channels. this bit will be cleared when all rfi events have been cleared in the individual channel event registers. 2 gunee global unequipped event: this bit will be set to one if an unequipped event (unee) is present in any of the channels. this bit will be cleared when all unequipped events have been cleared in the individual channel event registers. 1gslme global signal label mismatch event: this bit will be set to one if a sig- nal label mismatch event (slme) is present in any of the channels. this bit will be cleared when all signal label mismatch events have been cleared in the individual channel event registers. 0 grdie global rdi event: this bit will be set to one if a remote defect indication event (rdi-ve, rdi-vpde, rdi-vsde or rdi-vcde) is present in any of the channels. this bit will be cleared when all rdi events have been cleared in the individual channel event registers. address bit symbol description
- 113 of 154 - txc-04201b-mb ed. 4, september 2001 ds1mx7 txc-04201b data sheet proprietary transwitch corporation information for use solely by its customers 015 7 gxpm global external lais pin event mask: when set to one, all per chan- nel lais events (xpe) are masked from generating interrupts (overrides per channel mask when set). 6gdmpm global demap error event mask: when set to one, all per channel demap error events (dmpe) are masked from generating interrupts (overrides per channel mask when set). 5glosm global los event mask: when set to one, all per channel los events (lose) are masked from generating interrupts (overrides per channel mask when set). 4gmpm global map error event mask: when set to one, all per channel map error events (mpe) are masked from generating interrupts (overrides per channel mask when set). 3gdaism global ds1 ais event mask: when set to one, all per channel ds1 ais events (daise) are masked from generating interrupts (overrides per channel mask when set). 2grpom global received pointer justification counter overflow event mask: when set to one, all received pointer justification counter overflow events (rpoe) are masked from generating interrupts (overrides per channel mask when set). 1 gpgom global generated pointer justification counter overflow event mask: when set to one, all per channel generated pointer justification counter overflow events (pgoe) are masked from generating interrupts (overrides per channel mask when set). 0gcvom global code violation counter/crc-6 error counter overflow event mask: when set to one, all per channel code violation counter/crc-6 error counter overflow events (cvoe) are masked from generating inter- rupts (overrides per channel mask when set). address bit symbol description
- 114 of 154 - txc-04201b-mb ed. 4, september 2001 proprietary transwitch corporation information for use solely by its customers ds1mx7 txc-04201b data sheet 016 7 gfeom global rei (febe) counter overflow event mask: when set to one, all per channel rei (febe) counter overflow events (feoe) are masked from generating interrupts (overrides per channel mask when set). 6 gbipom global bip-2 error counter overflow event mask: when set to one, all per channel bip-2 error counter overflow events (bipoe) are masked from generating interrupts (overrides per channel mask when set). 5gvaism global vt ais event mask: when set to one, all per channel vt ais events (vaise) are masked from generating interrupts (overrides per channel mask when set). 4glopm global loss of pointer event mask: when set to one, all per channel lop events (lope) are masked from generating interrupts (overrides per channel mask when set). 3grfim global rfi event mask: when set to one, all per channel rfi events (rfie) are masked from generating interrupts (overrides per channel mask when set). 2 gunem global unequipped event mask: when set to one, all per channel unequipped events (unee) are masked from generating interrupts (over- rides per channel mask when set). 1gslmm global signal label mismatch event mask: when set to one, all per channel signal label mismatch events (slme) are masked from generat- ing interrupts (overrides per channel mask when set). 0grdim global rdi event mask: when set to one, all per channel rdi events (rdi-ve, rdi-vpde, rdi-vsde or rdi-vcde) are masked from gener- ating interrupts (overrides per channel mask when set). 017 7-0 d7-d0 command byte: this register contains the command byte for the serial port. the definitions of the bits will depend on the external device that is selected. the serial port control logic does not depend on the values in this register for operation. this byte is shifted out lsb (d0) first and rep- resents the first byte sent out at pin lsdo. 018 7-0 d7-d0 line interface serial data output: this register contains the serial data to be written to the selected line interface transceiver. the data is shifted out lsb (d0) first and represents the second byte sent out at pin lsdo. 019 7-0 d7-d0 line interface serial data input: this register contains the read back data from the line interface transceiver when a read operation is per- formed. the data is shifted in lsb (d0) first (see pin lsdi). address bit symbol description
- 115 of 154 - txc-04201b-mb ed. 4, september 2001 ds1mx7 txc-04201b data sheet proprietary transwitch corporation information for use solely by its customers 01a 7 bdcst broadcast: when this bit is set to one, serial port command and data output registers are broadcast to all seven line interface transceivers. 6r reserved: this bit must be set to zero. 5eprbsa prbs enable: when set to one, both the internal prbs analyzer and prbs generator are enabled. bits 2, 1 and 0 of this register select which channel ? s line decoder output is connected to the analyzer. the ana- lyzer ? s output is a one for bits prbss, prbse, prbspm and prbsfm as controlled by bits mprbse and eprbse. when this bit is set to zero or when the prbs analyzer is in lock, a zero is present in prbss, prbse, prbspm and prbsfm. to operate with an itu-t o.151 compliant 2 15 - 1 signal, the output of the prbs generator and/or the input to the prbs analyzer must be inverted. this is controlled by setting either or both txnrzp and rxnrzp in the global registers to a 1. 4ensrp enable serial port: when set to one, a single transfer takes place to the selected device (single or broadcast) in serial port mode. this bit must be toggled to zero before setting it to one for another transfer. 3r reserved: this bit must be set to zero. 2-0 ds1 channel number (0-6): when decoded with bit 0 as least signifi- cant bit the value (n=0-6) selected drives the active low chip select pin, lcs(n+1) . bdcst causes all seven lcsn pins to be selected in serial port mode. in prbs operation these bits select the channel to be monitored by the prbs analyzer. 01b 7 etbrcf enabletelecom bus receive clock fail: when set to one, the fault detector for dclk is enabled to drive pin iao if dclk fails. 6etbrsf enable telecom bus receive sync. fail: when set to one, the fault detector for dc1j1v1 is enabled to drive pin iao if dc1j1v1 fails. 5etbrpf enable telecom bus receive payload indicator fail: when set to one, the fault detector for dspe is enabled to drive pin iao if dspe fails. 4r reserved: this bit must be set to zero. 3emckf enable master clock fail: when set to one, the fault detector for srclk is enabled to drive pin iao if srclk fails. 2 etbtcf enable telecom bus transmit clock fail: when set to one, the fault detector for aclk is enabled to drive pin iao if aclk fails. 1 etbtsf enable telecom bus transmit sync. fail: when set to one, the fault detector for ac1j1v1 is enabled to drive pin iao if ac1j1v1 fails. 0 etbtpf enable telecom bus transmit payload indicator fail: when set to one, the fault detector for aspe is enabled to drive pin iao if aspe fails. address bit symbol description
- 116 of 154 - txc-04201b-mb ed. 4, september 2001 proprietary transwitch corporation information for use solely by its customers ds1mx7 txc-04201b data sheet 01c 7-4 r reserved: these bits must be set to zeros. 3etbrpy enable telecom bus receive parity error: when set to one, the parity error detector for the receive telecom bus is enabled to drive pin iao if a parity error is detected. 2eprbse enable prbs out of lock events: when set to one, the prbs ana- lyzer out of lock output is enabled to drive pin iao if the prbs analyzer goes out of lock. 1etbie enable telecom bus internal error: when set to one, the fault detector for telecom bus transmit internal collisions is enabled to drive pin iao if an internal collision occurs. 0etbxe enable telecom bus external error: when set to one, the fault detec- tor for telecom bus transmit external collisions is enabled to drive pin iao if an external collision occurs. 01d 7-0 ectl7 - ectl0 error control length: these bits meter the number of bip-2 or rei (febe) errors introduced when a channel ? s sfebe or sbipe bit is set to one. note that when a channel is set to idle (control bit idle is zero), this register has no effect on sfebe or sbipe and sfebe set to one or sbipe set to one will cause continuous rei-v (febe) or bip-2 errors to be sent. address bit symbol description ectl(7-0) resulting errors sent 00 1 frame 01 2 frames 02 3 frames fd 254 frames fe 255 frames ff continuous
- 117 of 154 - txc-04201b-mb ed. 4, september 2001 ds1mx7 txc-04201b data sheet proprietary transwitch corporation information for use solely by its customers 01e 7 tblpbk telecom bus loopback: when set to one, internally the telecom bus is placed in loopback with all 28 or 84 timeslots out of the mappers con- nected to the 28 or 84 timeslots of the demappers. aclk is the only tele- com bus signal used in telecom bus loopback; payload and reference signals are internally generated. this is an off-line test for the entire ds1mx7 with invalid data sent to the telecom bus; individual channels may be tested with the prbs generator / analyzer in this mode. 6ftbtpe force telecom bus transmit parity error: when set to one, the parity to the telecom bus (apar) is inverted, forcing continuous parity errors. 5tbtci telecom bus transmit clock inversion: this bit controls the active edge of the add bus clock (aclk). when set to a zero, the add bus input signals aspe and ac1j1v1 are sampled on the rising edge of aclk. the ad(0-7), apar and aadd output signals are clocked out to the add bus on the falling edge of the aclk. when set to a one, aspe and ac1j1v1 are sampled on the falling edge of aclk and ad(0-7), apar and aadd are clocked out on the rising edge. 4 tbrci telecom bus receive clock inversion: when set to zero, the active edge of dclk is the rising edge. when set to one, the active edge of dclk is the falling edge. 3tbdd telecom bus data delay: when set to zero, ad(0-7) and apar are pre- fetched and made available on the active edge of aclk as defined by aspe and ac1j1v1 (as shown in figure 10 and figure 11) with drive control as determined by drive pins daten and master (as described in the block diagram description and operation-telecom bus interface section). when set to one, ad(0-7) and apar are delayed by one full clock period of aclk; daten input must be delayed externally by one aclk period if it is to be used (e.g., daten controlled by aspe). 2-1 r reserved: these bits must be set to zeros. 0 rdid10 rdi de-bouncing equals 10: when set to zero, rdi is de-bounced for 5 vt superframes. this means it must be set for 5 vt superframes in a row to be declared as rdi for a channel and it must be cleared for 5 vt superframes in a row to be cleared. when set to one, rdi is de-bounced for 10 vt superframes. 01f - 03b 7-0 spare spare: these registers should not be accessed. 03c 7 dplllk digital phase lock loop lock: when set to one, the dpll fifo depth is determined by the value of dpll(6-0) in this register. this forces a constant frequency from all dplls (ltclkn). when set to zero, the dpll bias offset is determined by dpll(6-0). for normal ds1mx7 oper- ation set dplllk to zero. this control bit is for test purposes. 6-0 dpll6 - dpll0 digital phase lock loop control: when dplllk is set to zero, the value of dpll(6-0) is the ones complement of the dpll bias offset; for dpll(6-0) = 00 hex, the nominal design value is chosen. when dplllk is set to one, dpll(6-0) determines the fifo depth. for normal opera- tion, set to zero. these control bits are for test purposes. address bit symbol description
- 118 of 154 - txc-04201b-mb ed. 4, september 2001 proprietary transwitch corporation information for use solely by its customers ds1mx7 txc-04201b data sheet 03d 7-5 r reserved: these bits must be set to zeros. 4byplb bypass pointer leak buffer: when set to zero, the pointer leak buffer is enabled in all channels. when set to one, the pointer leak buffer is bypassed. for normal operation, set this bit to zero. this control bit is for test purposes. 3prbsck prbs clock: when set to zero, srclk is selected as the source of prbs clock. this bit is used for manufacturing tests; do not set it to a 1. 2tmdis threshold modulator disable: when set to zero, the threshold modula- tor is enabled. when set to one, the threshold modulator is disabled. for normal operation this bit should be set to zero. this control bit is for test purposes and may not be available in future versions. 1, 0 c2ph(1-0) c2 stuff bit phase: when both bits are set to zero, normal threshold modulator phase is chosen for the c2 stuff bits. setting either or both of these bits to one chooses an alternate phase for the threshold modula- tor. for normal operation, both of these bits should be set to zero. these control bits are for test purposes and may not be available in future ver- sions. 03e 7 tbrckfm telecom bus receive clock fault monitor: this bit will be set to one if dclk loss of clock is present but the transition to this state did not occur in the last one-second interval as defined by t1si. this bit is cleared by writing it to zero or by t1si rising edge if the condition no longer exists and event bit tbrcke has been cleared. 6 tbrsnfm telecom bus receive sync. fault monitor: this bit will be set to one if dc1j1v1 loss of signal is present, but the transition to this state did not occur in the last one-second interval as defined by t1si. this bit is cleared by writing it to zero or by t1si rising edge if the condition no longer exists and event bit tbrsne has been cleared. 5tbrpafm telecom bus receive payload indicator fault monitor: this bit will be set to one if dspe loss of signal is present, but the transition to this state did not occur in the last one-second interval as defined by t1si. this bit is cleared by writing it to zero or by t1si rising edge if the condition no longer exists and event bit tbrpae has been cleared. 4r reserved: this bit must be set to zero. 3mckfm master clock fault monitor: this bit will be set to one if srclk loss of clock is present, but the transition to this state did not occur in the last one-second interval as defined by t1si. this bit is cleared by writing it to zero or by t1si rising edge if the condition no longer exists and event bit mcke has been cleared. 2tbtckfm telecom bus transmit clock fault monitor: this bit will be set to one if aclk loss of clock is present, but the transition to this state did not occur in the last one-second interval as defined by t1si. this bit is cleared by writing it to zero or by t1si rising edge if the condition no longer exists and event bit tbtcke has been cleared. address bit symbol description
- 119 of 154 - txc-04201b-mb ed. 4, september 2001 ds1mx7 txc-04201b data sheet proprietary transwitch corporation information for use solely by its customers 03e (cont.) 1tbtsnfm telecom bus transmit sync. fault monitor: this bit will be set to one if ac1j1v1 loss of signal is present, but the transition to this state did not occur in the last one-second interval as defined by t1si.this bit is cleared by writing it to zero or by t1si rising edge if the condition no longer exists and event bit tbtsne has been cleared. 0tbtpafm telecom bus transmit payload indicator fault monitor: this bit will be set to one if aspe loss of clock is present, but the transition to this state did not occur in the last one-second interval as defined by t1si. this bit is cleared by writing it to zero or by t1si rising edge if the condi- tion no longer exists and event bit tbtpae has been cleared. 03f 7-4 r reserved: these bits must be set to zeros. 3tbrpyfm telecom bus receive parity error fault monitor: this bit will be set to one if a parity error is present, but the transition to this state did not occur in the last one-second interval as defined by t1si.this bit is cleared by writing it to zero or by t1si rising edge if the condition no longer exists and event bit tbrpye has been cleared. 2 prbsfm prbs out of lock fault monitor: this bit will be set to one if a prbs out of lock is present, but the transition to this state did not occur in the last one-second interval as defined by t1si. this bit is cleared by writing it to zero or by t1si rising edge if the condition no longer exists and event bit prbse has been cleared. 1 tbiefm telecom bus internal error fault monitor: this bit will be set to one if an internal bus collision is present, but the transition to this state did not occur in the last one-second interval as defined by t1si. this bit is cleared by writing it to zero or by t1si rising edge if the condition no longer exists and event bit tbiee has been cleared. 0 tbxefm telecom bus external error fault monitor: this bit will be set to one if an external bus collision is present, but the transition to this state did not occur in the last one-second interval as defined by t1si. this bit is cleared by writing it to zero or by t1si rising edge if the condition no longer exists and event bit tbxee has been cleared. address bit symbol description
- 120 of 154 - txc-04201b-mb ed. 4, september 2001 proprietary transwitch corporation information for use solely by its customers ds1mx7 txc-04201b data sheet per channel control registers *note: in the address, x= 040h for ds1 channel 1; 080h for ds1 channel 2; 0c0h for ds1 channel 3; 100h for ds1 chan- nel 4; 140h for ds1 channel 5; 180h for ds1 channel 6; 1c0h for ds1 channel 7. address* bit symbol description x+00 7 idle set the channel to idle: when set to zero, the channel is powered down; all-zeros are substituted for the payload and overhead bytes except v5. either an all-zeros v5 may be sent, indicating an unequipped condition, or a valid v5 may be sent (unassigned); v5 is determined by per channel con- trol bits rdiis, febeis, sfebe, srdi and transmit signal label. for nor- mal operation, including sending vt ais, this bit should be set to one. note that for proper idle operation register txz7 (reg. x+39h) should also be set to 00h. 6explos external pin enables los: when set to one, lais active (as determined by rxnrzp) is treated as los from the decoder. set this bit to one if using an external decoder or external loss of clock detector. set this bit to zero if lais pin is unused or used for another purpose (e.g., interrupt from an external line transceiver). see sh2ais and los2ais below for logic (regis- ter x+01h). 5datacom datacom mode: this bit, in conjunction with mode0 and mode1, enables datacom mode. if mode1 is set to zero, this bit is disregarded. see mode0, mode1 in this register. 4enzc enable excess zeros count: when set to one, this bit will enable the bpv counter to also count excess zeros. when b8zs transcoding is enabled, 8 or more consecutive zeros is an error. when b8zs transcoding is disabled, 16 or more consecutive zeros is an error. 3 lcode line code select: when set to one and encod is set to one, b8zs is selected for coding and decoding. when set to zero and encod is set to one, ami is selected for coding and decoding. when encod is set to zero, this bit selects the signal level on tnegn. 2 encod enable codec: when set to one, the line coder and decoder are enabled if mode1 is set to zero with the code selected by lcode. when set to zero, or if mode1 is set to one, nrz is selected. encod lcode mode1 line code tnegn 1 0 0 ami per codec 1 1 0 b8zs per codec 0 0 0,1 nrz logic low 0 1 0,1 nrz logic high
- 121 of 154 - txc-04201b-mb ed. 4, september 2001 ds1mx7 txc-04201b data sheet proprietary transwitch corporation information for use solely by its customers x+00 (cont.) 1 0 mode1, mode0 mode of operation: these bits select among two byte-synchronous or datacom modes and the asynchronous mode. modified byte-synchronous/ datacom mode accepts clock and frame from the framer; in byte-synchro- nous/datacom mode, ds1mx7 supplies clock and frame for both direc- tions of transmission. x+01 7 sh2vais enable signaling highway to vt ais: when set to one and datacom set to zero, the ais bit on the signaling highway (rsigln) in byte-synchronous mode maps to vt ais. 6los2ais enable los to vt or ds1 ais: when set to one, los from the ds1 side maps to vt ais (byte-synchronous; see sh2vais for logic) or ds1 ais. address* bit symbol description mode1 mode0 datacom line code mapping mode 0 0 - ami, b8zs, nrz asynchronous 0 1 - ami, b8zs, nrz asynchronous 1 0 0 nrz byte-synchronous 1 0 1 nrz byte-synchronous datacom 1 1 0 nrz modified byte-synchronous 1 1 1 nrz modified byte-synchronous datacom svtais =1 send vt ais + (send vt ais) mode1 (not async mode) los2ais (los to ais) explos (lais = los) pin lais rsigl ais bits = sh2vais (ais = sig hwy) datacom (not datacom mode) ais2vais (ds1 ais to vt a s) ds1 ais (from decoder) mode0 (modified byte sync) loss of frame on rsync lof2vais (lof to vt ais & map error) =1 =1 =1 =1 =1 =0 =1 =1 =1 xpfm, xppm shdais = 1 daisfm, daispm =1 mpfm, mppm 1 & & & + + & & & =1 & / + && 1 =1 xps, xpe, daiss, daise, mps, mpe, legend: & = logical "and" + = logical "or" / = logical "not" mode1 = 0 (async.) + & explos = 1 (lais = los) & xps, xpe, los (from decoder) = 1 & encod = 1(decoder enabled) & + los2ais = 1 (los to ais) & / ds1 ais (from decoder) = 1 loss,lose, daiss, daise, sdaiss = 1 (send ds1 ais to system) send all-ones for ds1 info bits in vt lais pin high xpfm, xppm = 1 losfm, lospm = 1 daisfm, daispm = 1
- 122 of 154 - txc-04201b-mb ed. 4, september 2001 proprietary transwitch corporation information for use solely by its customers ds1mx7 txc-04201b data sheet x+01 (cont.) 5lof2vais enable loss of frame to vt ais and map error: when set to one, the loss of multiframe synchronization signal (rsyncn) maps to vt ais and is indicated as a map error (see sh2vais for logic). 4 crc6 enable crc-6 generation: when set to one in the true byte sync mode only, crc-6 is generated into the transmit vt payload. crc-6 is calculated on the received vt payload and compared with the received crc-6 code. 3 vais2ais enable vt ais to ds1 ais: when set to one, vt ais received in v1 and v2 is mapped to ds1 ais. 2 rfi2yel enable rfi to ds1 yellow: when set to one, rfi received in v5 is mapped to ds1 yellow on the signaling highway. if datacom is set to one, this bit is disregarded. 1yel2rfi enable ds1 yellow to rfi: when set to one, ds1 yellow on the signaling highway maps to rfi in v5 (see rfi2yel for logic). if datacom is set to one, this bit is disregarded. 0ais2vais enable ds1 ais to vt ais: when set to one, ds1 ais detected in the decoder (99.9% or more ones) maps to vt ais in the byte sync. mode (see sh2vais for logic). if datacom is set to one, this bit is disregarded. address* bit symbol description datacom =0 ais bits (not datacom mode) mode1 (not async mode) sdaisl (send ds1 ais to line) vais2ais (vt ais to ds1 ais) vt ais vt lop slm2ais (sig lbl mis to ds1 ais) sig lbl mis une2ais (unequip to ds1 ais) =1 =1 =1 =1 =1 =1 vaisfm, vaispm lops, lope, =1 & & + + =1 vaiss, vaise =1 uneq sig lbl signal fail tbrval (telecom bus rx slot not assigned) =1 =0 unefm, unepm =1 unes, unee send ds1 idle =0 =1 & (all-zeros to ds1 line) / & & & & & & / + lopfm, loppm =1 slms, slme, slmfm, slmpm + + tsigl =1 all-ones ds1 signal send ds1 ais srfi =1 (send rfi) yel2rfi (ds1 yellow to rfi) rsigl yellow bit mode1 (not async mode) =1 =1 =1 =1 =1 datacom (not datacom mode) rfi in rec v5 signal fail =0 =1 =1 =1 =0 send rfi vtais =0 shyel = 1 rfi2yel (rfi to ds1 yellow) syell (send ds1 yellow to line) =1 =1 =1 =1 & (tsigl yellow bit = 1) rfis, rfie, send ds1 yellow & & & & & + + (v5 bit 4 = 1) rfifm, rfipm = 1
- 123 of 154 - txc-04201b-mb ed. 4, september 2001 ds1mx7 txc-04201b data sheet proprietary transwitch corporation information for use solely by its customers x+02 7 srdi-vpd* send rdi-vpd: when set to one, rdi-vpd is sent continuously if rdiis is also set to one. see rdiis below for logic. set to zero if this channel is pro- grammed unequipped. 6 srdi-vsd* send rdi-vsd: when set to one, rdi-vsd is sent continuously if rdiis is also set to one. see rdiis below for logic. set to zero if this channel is pro- grammed unequipped. 5 srdi-vcd* send rdi-vcd: when set to one, rdi-vcd is sent continuously if rdiis is also set to one. see rdiis below for logic. set to zero if this channel is pro- grammed unequipped. 4r reserved: this bit must be set to zero. 3 rdiis rdi insert select: when set to zero, rdi-vxx is generated autonomously from either internally detected faults or from values input at the ring port. when set to one rdi-vxx is sent continuously if srdi-vxx is set to one. set to one if this channel is programmed unequipped. 2slm2ais enable signal label mismatch to ais: when set to one, a signal label mismatch detected maps to ds1 ais (see vais2ais above for logic). this bit should be set to one if this channel is programmed unequipped. * note: when forcing by microprocessor selection, set only one of the bits srdi-vpd, srdi-vsd and srdi-vcd to one at any given time, to retain proper alarm priority. address* bit symbol description signal fail =0 sig. lbl mismatch srdi-vpd vtais vtlop srdi-vsd sig lbl unequip. srdi-vcd =1 =1 =1 =1 =1 =1 1 ringen =1 rdiis =1 (input) rgrdi-vpd rgrdi-vsd (input) (input) rgrdi-vcd =1 & & & & & & & + & & & & + & / + / & + / / & + & + & + / / / & no defect "0:001" rdi-vpd "0:010" rdi-vsd "1:101" rdi-vcd "1:110" + rgrdi-vpd (output) rgrdi-vsd (output) rgrdi-vcd (output) v5 bit 8 z7 bits 5, 6, 7 in map dir. note: "w:xyz" = v5, bit 8: z7, bits 5, 6, 7
- 124 of 154 - txc-04201b-mb ed. 4, september 2001 proprietary transwitch corporation information for use solely by its customers ds1mx7 txc-04201b data sheet x+02 (cont) 1febeis rei (febe) insert select: when set to zero, rei (febe) is generated from received bip-2 errors or from the ring port input. when set to one, rei (febe) or bip-2 errors can be created with sfebe or spibe. the required rei (febe) value is always output at the ring port (rgfebe-v). the rei (febe) value appearing in the outgoing v5, bit 3 results from received bip-2 errors if ringen is set to zero or from the input ring port value, rgfebe-v, if ringen is set to one. 0 une2ais enable unequipped to ds1 ais: when set to one, an unequipped signal label received is mapped to ds1 ais (see vais2ais for logic). this bit should be set to a zero if this channel is unequipped. use sdais to force ais to ds1 line if required when une2ais is set to zero. x+03 7 sfebe send rei (febe): when set to one, rei (febe) is sent the number of times specified by ectl(0-7) if control bit febeis is set to one, control bit idle is set to one and if control bit ringen is set to zero. when set to one, rei (febe) is sent continuously if control bit febeis is set to one, control bit idle is set to zero and if control bit ringen is set to zero. if ringen is set to one, the febes from the ring port are placed in the outgoing v5, bit 3. 6sdaiss send ds1 ais to system: when set to one, ds1 ais (all-ones) is used for the vt1.5 or tu-11 payload in the map direction. 5sbipe send bip-2 errors: when set to one, inverted bip-2 is sent the number of times specified by ectl(0-7) if febeis is set to one. this bit must be cleared to zero and set again to send a second set of inverted bip-2. 4r reserved: this bit must be set to zero. 3sdaisl send ds1 ais to the ds1 line: when set to one, ds1 ais is sent out of the coder using nominal timing (derived from srclk by dividing by 31.5). 2syell send ds1 yellow: when set to one, ds1 yellow is sent on the signaling highway (tsigln) in byte-synchronous mode. if datacom is set to one, this bit is disregarded. 1srfi send rfi: when set to one, the rfi bit is set in v5. 0 svtais send vt ais: when set to one, vt ais is generated in the mapping direc- tion by generating an all-ones vt1.5 or tu-11. address* bit symbol description febeis =1 sbipe =1 bip-2 error & insert bip-2 in map dir. & increment bec (0-11) signal fail =0 sfebe =1 ringen =1 rgfebe-v (input) & & + / rgfebe-v (output) & & / + v5, bit 3 in map dir.
- 125 of 154 - txc-04201b-mb ed. 4, september 2001 ds1mx7 txc-04201b data sheet proprietary transwitch corporation information for use solely by its customers x+04 7 tbrval telecom bus receive valid: when set to one, the telecom bus receive slot (information to dd(0-7)), as defined by the rest of the bits in this regis- ter, is considered valid and this channel ? s vt1.5 or tu-11 reads the bus. when set to zero, this channel does not read the dd(0-7) bus, nor does it send data to the auxiliary port. 6-5 tel bus rx sts-1 # (1-3) telecom bus receive sts-1 number: these bits select the sts-1 if the configi pin is grounded. 4-2 tel bus rx vt group or tug # (1-7) telecom bus receive vt group or tug number: these bits select the vt group or tug. 1-0 tel bus rx vt or tu # (1-4) telecom bus receive vt or tu number: these bits select the individual vt or tu in the group or tug. address* bit symbol description bit 6 bit 5 sts-1 number 00 1 01 2 10 3 1 1 not valid - do not use bit 4 bit 3 bit 2 vt group or tug number 000 1 001 2 010 3 011 4 100 5 101 6 110 7 1 1 1 not valid - do not use bit 1 bit 0 vt or tu number 00 1 01 2 10 3 11 4
- 126 of 154 - txc-04201b-mb ed. 4, september 2001 proprietary transwitch corporation information for use solely by its customers ds1mx7 txc-04201b data sheet x+05 7 tbtval telecom bus transmit valid: when set to one, the telecom bus transmit slot (information from ad(0-7)), as defined by the rest of the bits in this reg- ister, is considered valid and this channel ? s vt1.5 or tu-11 drives the bus. when set to zero, this channel does not drive the ad(0-7) bus nor does it request data from the auxiliary port. 6-5 tel bus tx sts-1 # (1-3) telecom bus transmit sts-1 number: these bits select the sts-1 if the configi pin is grounded. 4-2 tel bus tx vt group or tug # (1-7) telecom bus transmit vt group or tug number: these bits select the vt group or tug. 1-0 tel bus tx vt or tu # (1-4) telecom bus transmit vt or tu number: these bits select the individual vt or tu in the group or tug. address* bit symbol description bit 6 bit 5 sts-1 number 00 1 01 2 10 3 1 1 not valid - do not use bit 4 bit 3 bit 2 vt group or tug number 000 1 001 2 010 3 011 4 100 5 101 6 110 7 111 1 bit 1 bit 0 vt or tu number 00 1 01 2 10 3 11 4
- 127 of 154 - txc-04201b-mb ed. 4, september 2001 ds1mx7 txc-04201b data sheet proprietary transwitch corporation information for use solely by its customers x+06 7-0 pl(8-1) pointer leak rate: these bits determine the rate at which a pointer move- ment is leaked out of the pointer leak buffer into the dpll. if pl(8-1) is set to 00h the maximum leak rate of one bit per 16 vt superframes (8 ms) is used, with each count decreasing the rate by 16 vt superframes (8 ms). the times shown in the table below apply when the pointer leak buffer (which is 40 bits) is 12 bits or more above or below center. when the pointer leak buffer is less than 12 bits above or below center, the time between bits leaked is twice that shown in the table. x+07 7 r reserved: this bit must be set to zero. 6-4 exp. sig. label (2-0) expected signal label: bits 6 through 4 correspond to bits 5 through 7 respectively of v5 (gr-253-core issue 2, fig. 3-25) received from the telecom bus. the signal label mismatch detector compares these bits with those received from the telecom bus. set to 000 for unequipped, to 010 for asynchronous operation, to 001 for equipped non-specific, or to 100 for byte-synchronous operation. 3r reserved: this bit must be set to zero. 2-0 tx sig. label (2-0) transmit signal label: bits 2 through 0 correspond to bits 5 through 7 respectively of v5 (gr-253-core issue 2, fig. 3-25) to be sent out on the te l e c o m b u s . address* bit symbol description pl8 - pl1 time between bits leaked from pointer leak buffer 00h 8 ms 01h 16 ms 02h 24 ms fdh 2,032 ms feh 2,040 ms ffh 2,048 ms
- 128 of 154 - txc-04201b-mb ed. 4, september 2001 proprietary transwitch corporation information for use solely by its customers ds1mx7 txc-04201b data sheet x+08 7 xpm external lais pin event mask: when set to one, this channel ? s lais events (xpe) are masked from generating interrupts (status and event not affected). 6dmpm demap error event mask: when set to one, this channel ? s demap error events (dmpe) are masked from generating interrupts (status and event not affected). 5losm los event mask: when set to one, this channel ? s los events (lose) are masked from generating interrupts (status and event not affected). 4mpm map error event mask: when set to one, this channel ? s map error events (mpe) are masked from generating interrupts (status and event not affected). 3daism ds1 ais event mask: when set to one, this channel ? s ds1 ais events (daise) are masked from generating interrupts (status and event not affected). 2rpom received pointer justification counter overflow event mask: when set to one, received pointer justification counter overflow events (rpoe) from this channel are masked from generating interrupts (status and event not affected). 1 pgom generated pointer justification counter overflow event mask: when set to one, this channel ? s generated pointer justification counter overflow events (pgoe) are masked from generating interrupts (status and event not affected). 0cvom code violation counter/crc-6 error counter overflow event mask: when set to one, this channel ? s code violation counter/crc-6 error counter overflow events (cvoe) are masked from generating interrupts (status and event not affected). x+09 7 feom rei (febe) counter overflow event mask: when set to one, this chan- nel ? s rei (febe) counter overflow events (feoe) are masked from gener- ating interrupts (status and event not affected). 6bipom bip-2 error counter overflow event mask: when set to one, this chan- nel ? s bip-2 error counter overflow events (bipoe) are masked from gener- ating interrupts (status and event not affected). 5vaism vt ais event mask: when set to one, this channel ? s vt ais events (vaise) are masked from generating interrupts (status and event not affected). 4lopm loss of pointer event mask: when set to one, this channel ? s lop events (lope) are masked from generating interrupts (status and event not affected). 3rfim rfi event mask: when set to one, this channel ? s rfi events (rfie) are masked from generating interrupts (status and event not affected). 2unem unequipped event mask: when set to one, this channel ? s unequipped events (unee) are masked from generating interrupts (status and event not affected). set to one when this channel is programmed unequipped. address* bit symbol description
- 129 of 154 - txc-04201b-mb ed. 4, september 2001 ds1mx7 txc-04201b data sheet proprietary transwitch corporation information for use solely by its customers x+09 (cont) 1slmm signal label mismatch event mask: when set to one, this channel ? s sig- nal label mismatch events (slme) are masked from generating interrupts (status and event not affected). set to one when this channel is pro- grammed unequipped. 0rdim rdi event mask: when set to one, this channel ? s rdi events (rdi_ve) are masked from generating interrupts (status and event not affected). x+0a 7-3 r reserved: these bits must be set to zeros. 2 rdi-vpdm rdi-vpd event mask: when set to one, this channels ? s rdi-vpd events (rdi-vpde) are masked from generating interrupts (status and event not affected). 1 rdi-vsdm rdi-vsd event mask: when set to one, this channels ? s rdi-vsd events (rdi-vsde) are masked from generating interrupts (status and event not affected). 0 rdi-vcdm rdi-vcd event mask: when set to one, this channels ? s rdi-vcd events (rdi-vcde) are masked from generating interrupts (status and event not affected). x+0b 7-5 r reserved: these bits must be set to zeros. 4ringen ring port enable: when set to one, the outgoing v5 rei (febe) and rdi-vxx values are accepted from the ring port input. see rdiis and febeis above for logic. information input at the ring port is readable by the microprocessor in register x+3ah. 3 obapen o-bits auxiliary port enable: when set to zero, register x+36h contains microprocessor-written data that will appear on ad(0-7). when set to one, the o-bit incoming at the auxiliary port will appear on ad(0-7) and will also be written in register x+36h for access by the microprocessor. 2 j2apen j2 auxiliary port enable: when set to zero, register x+37h contains microprocessor- written data that will appear on ad(0-7). when set to one, the j2 byte incoming at the auxiliary port will appear on ad(0-7) and will also be written in register x+37h for access by the microprocessor. 1z6apen z6/n2 auxiliary port enable: when set to zero, register x+38h contains microprocessor ? written data that will appear on ad(0-7). when set to one, the z6/n2 byte incoming at the auxiliary port will appear on ad(0-7) and will also be written in register x+38h for access by the microprocessor. 0z7apen z7/k4 auxiliary port enable: when set to zero, register x+39h contains microprocessor ? written data that will appear on ad(0-7). when set to one, the z7/k4 byte incoming at the auxiliary port will appear on ad(0-7) and will also be written in register x+39h for access by the microprocessor. when ringen is set to one, rdi insert is from the ring port even if this bit is set to one. address* bit symbol description
- 130 of 154 - txc-04201b-mb ed. 4, september 2001 proprietary transwitch corporation information for use solely by its customers ds1mx7 txc-04201b data sheet x+0c 7 dtlpbk ds1 tributary loopback: when set to one, the output of the line coder is looped to the input of the line decoder. clock, multiframe synchronization and signaling are also looped back. this loopback is useful for ds1mx7 self test with the prbs generator and analyzer. the ds1 tributary loop- back can only be used in the asynchronous and modified byte synchro- nous modes. 6dflpbk ds1 remote facility loopback: when set to one, the output of the decoder is looped to the input of the coder. clock, multiframe synchroniza- tion and signaling are also looped back. this loopback is used to provide remote facility loopback testing. 5rstch reset channel: when this bit is set to one, this channel is held in reset; it provides the same function that the reset register (005h) provides for all channels. 4 sprbs send prbs: when set to one, the output of the prbs generator is substi- tuted for the output of the decoder for this channel. this bit, used in con- junction with dtlpbk (ds1 facility loopback), bit 7 in this register, tblpbk (telecom bus loopback) at register 01eh bit 7, eprbsa (enable prbs generator/analyzer) at register 01ah bit 5, which must be set to one, and the ds1 channel number, provides a self test of this channel. 3-0 r reserved: these bits must be set to zeros. x+0d - x+0f 7-0 r reserved: these registers should not be accessed. address* bit symbol description
- 131 of 154 - txc-04201b-mb ed. 4, september 2001 ds1mx7 txc-04201b data sheet proprietary transwitch corporation information for use solely by its customers per channel status registers address* bit symbol description x+10 7 xps external pin status: when this bit is a one, the external pin (lais) for this channel is active per rxnrzp (lais is high if rxnrzp is zero or lais is low if rxnrzp is one). 6dmps demap error status: when this bit is a one, a fault (e.g. internal fifo overflow/underflow) is occurring in the desynchronizer for this channel. 5loss loss of signal status: when this bit is a one, los is currently being detected in this channel. detection of los is based on no pulses being a logic low on both the rposn and rnegn pins for 175 75 contiguous clock cycles of lrclkn. los exits on 12.5% or greater ones density for 175 75 contiguous pulse positions. los does not function in nrz mode. 4mps map error status: when this bit is a one, a map error is occurring in this channel. if bit lof2vais is one, this bit represents a loss of multiframe input in byte-synchronous operation. 3daiss ds1 ais status: when this bit is a one, ds1 ais is being detected in the line decoder for this channel. ds1 ais is declared if 99.9% ones are detected for between 3 and 75 milliseconds. ais exits on less than 99.9% all-ones for between 3 and 75 milliseconds. 2rpos received pointer justification counter overflow status: when this bit is a one, the received pointer justification counter for this channel has over- flowed. 1 pgos generated pointer justification counter overflow status: when this bit is a one, the generated pointer justification counter has overflowed for this channel. 0cvos code violation counter/crc-6 error counter overflow status: when this bit is a one, the code violation counter/crc-6 error counter for this channel has overflowed.
- 132 of 154 - txc-04201b-mb ed. 4, september 2001 proprietary transwitch corporation information for use solely by its customers ds1mx7 txc-04201b data sheet x+11 7 feos rei (febe) counter overflow status: when this bit is a one, the rei (febe) counter for this channel has overflowed. 6bipos bip-2 error counter overflow status: when this bit is a one, the bip-2 error counter for this channel has overflowed. 5vaiss vt ais status: when this bit is a one, vt ais is currently being detected for this channel. vt ais is declared if 3 consecutive v1 and v2 bytes are all-ones. vt ais is removed when a valid vt pointer is received with valid ss-bits, with a ndf, or with 3 consecutive vt superframes having a valid vt pointer and valid ss-bits with no ndf. 4lops lop status: when this bit a one, loss of pointer is currently being detected for this channel. lop is entered with 8 consecutive ndf enables or invalid pointers. lop is exited to normal if 3 consecutive valid vt pointers are received with valid ss-bits. lop is exited to ais if 3 consecutive all-ones pointers are received. 3rfis rfi status: when this bit is a one, the receive failure indication has been de-bounced for 10 consecutive v5 bytes and is set for this channel. rfi is only a valid indication in byte-synchronous modes of operation. this bit will clear if rfi is reset in 10 consecutive v5 bytes. 2 unes unequipped status: this bit reflects the current status of the receive sig- nal label for this channel (de-bounced for 5 consecutive v5 bytes) with respect to unequipped (signal label = 000). when this bit is a one, the incoming vt1.5 or tu-11 is unequipped. this bit will clear if 5 consecutive v5 bytes do not have an all-zero signal label. 1slms signal label mismatch status: when this bit is set to a one, a mismatch has been de-bounced and detected for 5 consecutive v5 bytes between the expected signal label and the received signal label for this channel. a received or expected value of ? equipped non-specific ? (signal label = 001) is not a mismatch for any non-zero signal label. this bit will clear if 5 consec- utive v5 bytes match. an unequipped signal label (signal label = 000) received will cause this bit to be set unless the expected signal label (bits 6-4 of register x+07h) is set to unequipped. 0 rdi-vs rdi-v status: when this bit is a one, a remote defect indication (from equipment that does not support enhanced rdi) has been de-bounced for 5 or 10 consecutive v5 bytes and detected for this channel. this bit will clear if rdi is reset for 5 or 10 consecutive v5 bytes. rdid10 selects the de-bounce period. address* bit symbol description
- 133 of 154 - txc-04201b-mb ed. 4, september 2001 ds1mx7 txc-04201b data sheet proprietary transwitch corporation information for use solely by its customers x+12 7-3 r reserved: these bits have indeterminate status on read. 2 rdi-vpds rdi-vpd status: when this bit is set to one, a vt remote payload defect indication has been de-bounced for 5 or 10 consecutive z7/k4 bytes and detected for this channel. this bit will clear if rdi-vpd is not received for 5 or 10 consecutive z7/k4 bytes. rdid10 selects the de-bounce period. 1 rdi-vsds rdi-vsd status: when this bit is set to one, a vt remote server defect indication has been de-bounced for 5 or 10 consecutive z7/k4 bytes and detected for this channel. this bit will clear if rdi-vsd is not received for 5 or 10 consecutive z7/k4 bytes. rdid10 selects the de-bounce period. 0 rdi-vcds rdi-vcd status: when this bit is set to one, a vt remote connectivity defect indication has been de-bounced for 5 or 10 consecutive z7/k4 bytes and detected for this channel. this bit will clear if rdi-vcd is not received for 5 or 10 consecutive z7/k4 bytes. rdid10 selects the de- bounce period. x+13 7-0 spare spare: this register should not be accessed. x+14 7 xpe external pin event: this bit will be set to one by the ds1mx7 when the active edge of the external pin (lais) for this channel (xps), as deter- mined by rise and fall, and the sense as determined by rxnrzp, has occurred. this bit is cleared by writing a zero to this bit location or by t1si if enpmfm is set to one. 6dmpe demap error event: this bit will be set to one by the ds1mx7 when the active edge of a demap error for this channel (dmps), as determined by rise and fall, has occurred. this bit is cleared by writing a zero to this bit location or by t1si if enpmfm is set to one. 5lose loss of signal event: this bit will be set to one by the ds1mx7 when the active edge of an los for this channel (loss), as determined by rise and fall, has occurred. this bit is cleared by writing a zero to this bit loca- tion or by t1si if enpmfm is set to one. 4mpe map error event: this bit will be set to one by the ds1mx7 when the active edge of a map error for this channel (mps), as determined by rise and fall, has occurred. this bit is cleared by writing a zero to this bit loca- tion or by t1si if enpmfm is set to one. 3daise ds1 ais event: this bit will be set to one by the ds1mx7 when the active edge of a ds1 ais for this channel (daiss), as determined by rise and fall, has occurred. this bit is cleared by writing a zero to this bit location or by t1si if enpmfm is set to one. 2rpoe received pointer justification counter overflow event: this bit will be set to one by the ds1mx7 when the active edge of a received pointer justi- fication counter overflow for this channel (rpos), as determined by rise and fall, has occurred. this bit is cleared by writing a zero to this bit loca- tion or by t1si if enpmfm is set to one. address* bit symbol description
- 134 of 154 - txc-04201b-mb ed. 4, september 2001 proprietary transwitch corporation information for use solely by its customers ds1mx7 txc-04201b data sheet x+14 (cont.) 1 pgoe generated pointer justification counter overflow event: this bit will be set to one by the ds1mx7 when the active edge of a generated pointer justification counter overflow for this channel (pgos), as determined by rise and fall, has occurred. this bit is cleared by writing a zero to this bit location or by t1si if enpmfm is set to one. 0cvoe code violation counter/crc-6 error counter overflow event: this bit will be set to one by the ds1mx7 when the active edge of a code violation counter/crc-6 error counter overflow for this channel (cvos), as deter- mined by rise and fall, has occurred. this bit is cleared by writing a zero to this bit location or by t1si if enpmfm is set to one. x+15 7 feoe rei (febe) counter overflow event: this bit will be set to one by the ds1mx7 when the active edge of a rei (febe) counter overflow for this channel (feos), as determined by rise and fall, has occurred. this bit is cleared by writing a zero to this bit location or by t1si if enpmfm is set to one. 6bipoe bip-2 error counter overflow event: this bit will be set to one by the ds1mx7 when the active edge of a bip-2 error counter overflow for this channel (bipos), as determined by rise and fall, has occurred. this bit is cleared by writing a zero to this bit location or by t1si if enpmfm is set to one. 5vaise vt ais event: this bit will be set to one by the ds1mx7 when the active edge of a vt ais for this channel (vaiss), as determined by rise and fall, has occurred. this bit is cleared by writing a zero to this bit location or by t1si if enpmfm is set to one. 4lope lop event: this bit will be set to one by the ds1mx7 when the active edge of a lop for this channel (lops), as determined by rise and fall, has occurred. this bit is cleared by writing a zero to this bit location or by t1si if enpmfm is set to one. 3rfie rfi event: this bit will be set to one by the ds1mx7 when the active edge of an rfi for this channel (rfis), as determined by rise and fall, has occurred. this bit is cleared by writing a zero to this bit location or by t1si if enpmfm is set to one. 2 unee unequipped event: this bit will be set to one by the ds1mx7 when the active edge of an unequipped signal label for this channel (unes), as determined by rise and fall, has occurred. this bit is cleared by writing a zero to this bit location or by t1si if enpmfm is set to one. 1slme signal label mismatch event: this bit will be set to one by the ds1mx7 when the active edge of a signal label mismatch for this channel (slms), as determined by rise and fall, has occurred. this bit is cleared by writ- ing a zero to this bit location or by t1si if enpmfm is set to one. 0 rdi-ve rdi-v event: this bit will be set to one by the ds1mx7 when the active edge of an rdi for this channel (rdi-vs), as determined by rise and fall, has occurred. this bit is cleared by writing a zero to this bit location or by t1si if enpmfm is set to one. address* bit symbol description
- 135 of 154 - txc-04201b-mb ed. 4, september 2001 ds1mx7 txc-04201b data sheet proprietary transwitch corporation information for use solely by its customers x+16 7-3 r reserved: these bits must be set to zeros. 2 rdi-vpde rdi-vpd event: this bit will be set to one when the active edge of an rdi-vpd for this channel (rdi-vpds), as determined by rise and fall, has occurred. this bit is cleared by writing a zero to this bit location or by t1si if enpmfm is set to one. 1 rdi-vsde rdi-vsd event: this bit will be set to one when the active edge of an rdi-vsd for this channel (rdi-vsds), as determined by rise and fall, has occurred. this bit is cleared by writing a zero to this bit location or by t1si if enpmfm is set to one. 0 rdi-vcde rdi-vcd event: this bit will be set to one when the active edge of an rdi-vcd for this channel (rdi-vcds), as determined by rise and fall, has occurred. this bit is cleared by writing a zero to this bit location or by t1si if enpmfm is set to one. x+17 7-0 spare spare: this register should not be accessed. x+18 7 xppm external pin performance monitor: this bit will be set to one by the ds1mx7 if an external pin event (xpe) has occurred in the last one-sec- ond interval as defined by t1si, if enpmfm is set to one. this bit may be cleared by writing it to a zero. 6dmppm demap error performance monitor: this bit will be set to one by the ds1mx7 if a demap error event (dmpe) has occurred in the last one-sec- ond interval as defined by t1si, if enpmfm is set to one. this bit may be cleared by writing it to a zero. 5lospm loss of signal performance monitor: this bit will be set to one by the ds1mx7 if an los event (lose) has occurred in the last one-second interval as defined by t1si, if enpmfm is set to one. this bit may be cleared by writing it to a zero. 4mppm map error performance monitor: this bit will be set to one by the ds1mx7 if a map error event (mpe) has occurred in the last one-second interval as defined by t1si, if enpmfm is set to one. this bit may be cleared by writing it to a zero. 3 daispm ds1 ais performance monitor: this bit will be set to one by the ds1mx7 if a ds1 ais event (daise) has occurred in the last one-second interval as defined by t1si, if enpmfm is set to one. this bit may be cleared by writ- ing it to a zero. 2 rpopm received pointer justification counter overflow performance moni- tor: this bit will be set to one by the ds1mx7 if a received pointer justifica- tion counter overflow event (rpoe) has occurred in the last one-second interval as defined by t1si, if enpmfm is set to one. this bit may be cleared by writing it to a zero. 1 pgopm generated pointer justification counter overflow performance moni- tor: this bit will be set to one by the ds1mx7 if a generated pointer justifi- cation counter overflow event (pgoe) has occurred in the last one-second interval as defined by t1si, if enpmfm is set to one. this bit may be cleared by writing it to a zero. address* bit symbol description
- 136 of 154 - txc-04201b-mb ed. 4, september 2001 proprietary transwitch corporation information for use solely by its customers ds1mx7 txc-04201b data sheet x+18 (cont.) 0cvopm code violation counter/crc-6 error counter overflow performance monitor: this bit will be set to one by the ds1mx7 if a code violation counter/crc-6 error counter overflow event (cvoe) has occurred in the last one-second interval as defined by t1si, if enpmfm is set to one. this bit may be cleared by writing it to a zero. x+19 7 feopm rei (febe) counter overflow performance monitor: this bit will be set to one by the ds1mx7 if a rei (febe) counter overflow event (feoe) has occurred in the last one-second interval as defined by t1si, if enpmfm is set to one. this bit may be cleared by writing it to a zero. 6bipopm bip-2 error counter overflow performance monitor: this bit will be set to one by the ds1mx7 if a bip-2 counter overflow event (bipoe) has occurred in the last one-second interval as defined by t1si, if enpmfm is set to one. this bit may be cleared by writing it to a zero. 5vaispm vt ais performance monitor: this bit will be set to one by the ds1mx7 if a vt ais event (vaise) has occurred in the last one-second interval as defined by t1si, if enpmfm is set to one. this bit may be cleared by writ- ing it to a zero. 4loppm lop performance monitor: this bit will be set to one by the ds1mx7 if an lop event (lope) has occurred in the last one-second interval as defined by t1si, if enpmfm is set to one. this bit may be cleared by writ- ing it to a zero. 3rfipm rfi performance monitor: this bit will be set to one by the ds1mx7 if an rfi event (rfie) has occurred in the last one-second interval as defined by t1si, if enpmfm is set to one. this bit may be cleared by writing it to a zero. 2unepm unequipped performance monitor: this bit will be set to one by the ds1mx7 if an unequipped signal label event (unee) has occurred in the last one-second interval as defined by t1si, if enpmfm is set to one. this bit may be cleared by writing it to a zero. 1slmpm signal label mismatch performance monitor: this bit will be set to one by the ds1mx7 if a signal label mismatch event (slme) has occurred in the last one-second interval as defined by t1si, if enpmfm is set to one. this bit may be cleared by writing it to a zero. 0 rdi-vpm rdi-v performance monitor: this bit will be set to one by the ds1mx7 if an rdi event (rdi-ve) has occurred in the last one-second interval as defined by t1si, if enpmfm is set to one. this bit may be cleared by writ- ing it to a zero. address* bit symbol description
- 137 of 154 - txc-04201b-mb ed. 4, september 2001 ds1mx7 txc-04201b data sheet proprietary transwitch corporation information for use solely by its customers x+1a 7-3 r reserved: these bits must be set to zeros. 2 rdi-vpdpm rdi-vpd performance monitor: this bit will be set to one, if an rdi-vpd event (rdi-vpde) has occurred in the last one-second interval as defined by t1si, if enpmfm is set to one. this bit may be cleared by writing it to a zero. 1 rdi-vsdpm rdi-vsd performance monitor: this bit will be set to one, if an rdi-vsd event (rdi-vsde) has occurred in the last one-second interval as defined by t1si, if enpmfm is set to one. this bit may be cleared by writing it to a zero. 0 rdi-vcdpm rdi-vcd performance monitor: this bit will be set to one, if an rdi-vcd event (rdi-vcde) has occurred in the last one-second interval as defined by t1si, if enpmfm is set to one. this bit may be cleared by writing it to a zero. x+1b 7-0 spare spare: this register should not be accessed. x+1c 7 xpfm external pin fault monitor: this bit will be set to one by the ds1mx7 if an external pin event (xpe) is active but the transition to the active state has not occurred in the last one-second interval as defined by t1si, if enpmfm is set to one. this bit may be cleared by writing it to a zero. 6dmpfm demap error fault monitor: this bit will be set to one by the ds1mx7 if a demap error event (dmpe) is active but the transition to the active state has not occurred in the last one-second interval as defined by t1si, if enpmfm is set to one. this bit may be cleared by writing it to a zero. 5losfm loss of signal fault monitor: this bit will be set to one by the ds1mx7 if an los event (lose) is active but the transition to the active state has not occurred in the last one-second interval as defined by t1si, if enpmfm is set to one. this bit may be cleared by writing it to a zero. 4mpfm map error fault monitor: this bit will be set to one by the ds1mx7 if a map error event (mpe) is active but the transition to the active state has not occurred in the last one-second interval as defined by t1si, if enpmfm is set to one. this bit may be cleared by writing it to a zero. 3daisfm ds1 ais fault monitor: this bit will be set to one by the ds1mx7 if a ds1 ais event (daise) is active but the transition to the active state has not occurred in the last one-second interval as defined by t1si, if enpmfm is set to one. this bit may be cleared by writing it to a zero. 2rpofm received pointer justification counter overflow fault monitor: this bit will be set to one by the ds1mx7 if a received pointer justification counter overflow event (rpoe) is active but the transition to the active state has not occurred in the last one-second interval as defined by t1si, if enpmfm is set to one. this bit may be cleared by writing it to a zero. 1pgofm generated pointer justification counter overflow fault monitor: this bit will be set to one by the ds1mx7 if a generated pointer justification counter overflow event (pgoe) is active but the transition to the active state has not occurred in the last one-second interval as defined by t1si, if enpmfm is set to one. this bit may be cleared by writing it to a zero. address* bit symbol description
- 138 of 154 - txc-04201b-mb ed. 4, september 2001 proprietary transwitch corporation information for use solely by its customers ds1mx7 txc-04201b data sheet x+1c (cont.) 0cvofm code violation counter/crc-6 error counter overflow fault monitor: this bit will be set to one by the ds1mx7 if a code violation counter/crc-6 error counter overflow event (cvoe) is active but the transition to the active state has not occurred in the last one-second interval as defined by t1si, if enpmfm is set to one. this bit may be cleared by writing it to a zero. x+1d 7 feofm rei (febe) counter overflow fault monitor: this bit will be set to one by the ds1mx7 if a rei (febe) counter overflow event (feoe) is active but the transition to the active state has not occurred in the last one-second interval as defined by t1si, if enpmfm is set to one. this bit may be cleared by writing it to a zero. 6bipofm bip-2 error counter overflow fault monitor: this bit will be set to one by the ds1mx7 if a bip-2 error counter overflow event (bipoe) is active but the transition to the active state has not occurred in the last one-second interval as defined by t1si, if enpmfm is set to one. this bit may be cleared by writing it to a zero. 5 vaisfm vt ais fault monitor: this bit will be set to one by the ds1mx7 if a vt ais event (vaise) is active but the transition to the active state has not occurred in the last one-second interval as defined by t1si, if enpmfm is set to one. this bit may be cleared by writing it to a zero. 4lopfm lop fault monitor: this bit will be set to one by the ds1mx7 if a lop event (lope) is active but the transition to the active state has not occurred in the last one-second interval as defined by t1si, if enpmfm is set to one. this bit may be cleared by writing it to a zero. 3 rfifm rfi fault monitor: this bit will be set to one by the ds1mx7 if an rfi event (rfie) is active but the transition to the active state has not occurred in the last one-second interval as defined by t1si, if enpmfm is set to one. this bit may be cleared by writing it to a zero. 2 unefm unequipped fault monitor: this bit will be set to one by the ds1mx7 if an unequipped signal label event (unee) is active but the transition to the active state has not occurred in the last one-second interval as defined by t1si, if enpmfm is set to one. this bit may be cleared by writing it to a zero. 1slmfm signal label mismatch fault monitor: this bit will be set to one by the ds1mx7 if a signal label mismatch event (slme) is active but the transi- tion to the active state has not occurred in the last one-second interval as defined by t1si, if enpmfm is set to one. this bit may be cleared by writ- ing it to a zero. 0 rdi-vfm rdi-v fault monitor: this bit will be set to one by the ds1mx7 if an rdi event (rdi-ve) is active but the transition to the active state has not occurred in the last one-second interval as defined by t1si, if enpmfm is set to one. this bit may be cleared by writing it to a zero. address* bit symbol description
- 139 of 154 - txc-04201b-mb ed. 4, september 2001 ds1mx7 txc-04201b data sheet proprietary transwitch corporation information for use solely by its customers x+1e 7-3 reserved reserved: these bits must be set to zeros. 2rdi-vpdfm rdi-vpd fault monitor: this bit will be set to one if an rdi-vpd event (rdi-vpde) is active but the transition to the active state has not occurred in the last one-second interval as defined by t1si, if enpmfm is set to one. this bit may be cleared by writing it to a zero. 1rdi-vsdfm rdi-vsd fault monitor: this bit will be set to one if an rdi-vsd event (rdi-vsde) is active but the transition to the active state has not occurred in the last one-second interval as defined by t1si, if enpmfm is set to one. this bit may be cleared by writing it to a zero. 0 rdi-vcdfm rdi-vcd fault monitor: this bit will be set to one if an rdi-vcd event (rdi-vcde) is active but the transition to the active state has not occurred in the last one-second interval as defined by t1si, if enpmfm is set to one. this bit may be cleared by writing it to a zero. x+1f 7-0 spare spare: this register should not be accessed. x+20 7 shdais signaling highway ds1 ais status: this bit is a one if a ds1 ais indica- tion is received from the signaling highway in byte-synchronous mode only. 6shyel signaling highway yellow: this bit is a one if a ds1 yellow indication is received from the signaling highway in byte-synchronous mode only. 5r reserved: this bit reads out as zero. 4, 3 rxss1, rxss0 received ss-bits: these two bits represent the ss-bits (ss-bit 1 and ss-bit 0 respectively) received from the vt1.5 or tu-11 v1 and v2 bytes. 2-0 rx signal label (2-0) receive signal label: these bits represent the signal label received from the v5 byte for this channel. bits 2 through 0 correspond to bits 5 through 7 respectively of the v5 byte received from the telecom bus. x+21 7-0 spare spare: this register should not be accessed. x+22 7-0 cvc (7-0)/ crc6(7-0) line code violation counter/crc-6 error counter: this is the lower byte of a 12-bit free running counter which will increment by one for each received line code violation. if excessive zeros counting is enabled (enzc is set to one) they will also be counted with the line code errors. this counter can be cleared by writing its value to zero. if the counter overflows the cvos and cvoe bits (plus cvopm and cvofm bits if enpmfm is set) will be set. if enpmfm is set, this counter ? s latched value is updated every one-second at lcvc(7-0) and this counter is subsequently cleared for the next one-second interval. when crc-6 (x+01h, bit 4) is set, this counter is used as the crc-6 error counter lower byte in byte-synchronous modes only. address* bit symbol description
- 140 of 154 - txc-04201b-mb ed. 4, september 2001 proprietary transwitch corporation information for use solely by its customers ds1mx7 txc-04201b data sheet x+23 7-4 r reserved: these bits must be set to zeros. 3-0 cvc (11-8)/ crc6(11-8) line code violation counter/crc-6 error counter: this is the upper nibble of a 12-bit free running counter which will increment by one for each received line code violation. if excessive zeros counting is enabled (enzc is set to one) they will also be counted with the line code errors. this counter can be cleared by writing its value to zero. if the counter overflows the cvos and cvoe bits (plus cvopm and cvofm bits if enpmfm is set) will be set. if enpmfm is set, this counter ? s latched value is updated every one-second at lcvc(11-8) and this counter is subsequently cleared for the next one-second interval. when crc-6 (x+01h, bit 4) is set, this counter is used as crc-6 error counter upper nibble in byte-synchronous modes only. x+24 7-4 rx ptr. inc. counter pointer increments received counter: this four-bit counter represents the number of vt pointer increments received for this channel. this counter can be cleared by writing its value to zero. if the counter overflows the rpos and rpoe bits (plus rpopm and rpofm bits if enpmfm is set) will be set. if enpmfm is set, this counter ? s latched value is updated every one-second at address x+23h and this counter is subsequently cleared for the next one-second interval. 3-0 rx ptr. dec. counter pointer decrements received counter: this four-bit counter represents the number of vt pointer decrements received for this channel. this counter can be cleared by writing its value to zero. if the counter overflows the rpos and rpoe bits (plus rpopm and rpofm bits if enpmfm is set) will be set. if enpmfm is set, this counter ? s latched value is updated every one-second at address x+23h and this counter is subsequently cleared for the next one-second interval. x+25 7-4 ptr. inc. gen. counter pointer increments generated counter: this four-bit counter represents the number of vt pointer increments generated by this channel for byte- synchronous mode of operation. this counter can be cleared by writing its value to zero. if the counter overflows the pgos and pgoe bits (plus pgopm and pgofm bits if enpmfm is set) will be set. if enpmfm is set, this counter ? s latched value is updated every one-second at address x+24h and this counter is subsequently cleared for the next one-second interval. 3-0 ptr dec. gen. counter pointer decrements generated counter: this four-bit counter repre- sents the number of vt pointer decrements received for this channel. this counter can be cleared by writing its value to zero. if the counter overflows the pgos and pgoe bits (plus pgopm and pgofm bits if enpmfm is set) will be set. if enpmfm is set, this counter ? s latched value is updated every one-second at address x+24h and this counter is subsequently cleared for the next one-second interval. address* bit symbol description
- 141 of 154 - txc-04201b-mb ed. 4, september 2001 ds1mx7 txc-04201b data sheet proprietary transwitch corporation information for use solely by its customers x+26 7-0 bec (7-0) bip-2 error counter: this is the lower byte of a 12-bit free running counter. when control bit sdh is set to zero, it will increment by one for each bip-2 error received. when sdh is set to one, it will increment block counts of bip-2 errors. this counter can be cleared by writing its value to zero. if the counter overflows the bipos and bipoe bits (plus bipopm and bipofm bits if enpmfm is set) will be set. if enpmfm is set, this counter ? s latched value is updated every one-second at lbec(7-0) and this counter is subsequently cleared for the next one-second interval. x+27 7-4 r reserved: these bits must be set to zeros. 3-0 bec (11-8) bip-2 error counter: this is the upper nibble of a 12-bit free running counter. when control sdh is set to zero, it will increment by one for each bip-2 error received. when sdh is set to one, it will increment block counts of bip-2 errors. this counter can be cleared by writing its value to zero. if the counter overflows the bipos and bipoe bits (plus bipopm and bipofm bits if enpmfm is set) will be set. if enpmfm is set, this counter ? s latched value is updated every one-second at lbec(11-8) and this counter is subsequently cleared for the next one-second interval. x+28 7-0 fec (7-0) rei (febe) counter: this is the lower byte of a 12-bit free running counter which will increment by one for each far end block error received. this counter can be cleared by writing its value to zero. if the counter over- flows the feos and feoe bits (plus feopm and feofm bits if enpmfm is set) will be set. if enpmfm is set, this counter ? s latched value is updated every one-second at lfec(7-0) and this counter is subsequently cleared for the next one-second interval. x+29 7-4 r reserved: these bits must be set to zeros. 3-0 fec (11-8) rei (febe) counter: this is the upper nibble of a 12-bit free running counter which will increment by one for each far end block error received. this counter can be cleared by writing its value to zero. if the counter over- flows the feos and feoe bits (plus feopm and feofm bits if enpmfm is set) will be set. if enpmfm is set, this counter ? s latched value is updated every one-second at lfec(11-8) and this counter is subsequently cleared for the next one-second interval. x+2a 7-0 lcvc (7-0)/ lcrc6(7-0) latched line code violation counter / crc-6 error counter: this is the lower byte of a 12-bit shadow register which is updated from the line code violation counter once a second. the one-second interval is derived from the external one-second input, t1si. when crc6 (x+01h, bit 4) is set, this counter is used as crc-6 error counter lower byte in byte-syn- chronous modes only. x+2b 7-4 r reserved: these bits must be set to zeros. 3-0 lcvc (11-8)/ lcrc6(11-8) latched line code violation counter / crc-6 error counter: this is the upper nibble of a 12-bit shadow register which is updated from the line code violation counter once a second. the one-second interval is derived from the external one-second input, t1si. when crc6 (x+01h, bit 4) is set, this counter is used as crc-6 error counter upper nibble in byte-syn- chronous modes only. address* bit symbol description
- 142 of 154 - txc-04201b-mb ed. 4, september 2001 proprietary transwitch corporation information for use solely by its customers ds1mx7 txc-04201b data sheet x+2c 7-4 latched rx ptr. inc. counter latched pointer increments received counter: this is the 4-bit shadow register which is updated from the pointer increments received counter once a second. the one-second interval is derived from the external one- second input, t1si. 3-0 latched rx ptr. dec. counter latched pointer decrements received counter: this is the 4-bit shadow register which is updated from the pointer decrements received counter once a second. the one-second interval is derived from the exter- nal one-second input, t1si. x+2d 7-4 latched ptr. inc. gen. counter latched pointer increments generated counter: this is the 4-bit shadow register which is updated from the pointer increments generated counter once a second. the one-second interval is derived from the exter- nal one-second input, t1si. 3-0 latched ptr dec. gen. counter latched pointer decrements generated counter: this is the 4-bit shadow register which is updated from the pointer decrements generated counter once a second. the one-second interval is derived from the exter- nal one-second input, t1si. x+2e 7-0 lbec (7-0) latched bip-2 error counter: this is the lower byte of a 12-bit shadow register which is updated from the bip-2 error counter once a second. the one-second interval is derived from the external one-second input, t1si. x+2f 7-4 r reserved: these bits must be set to zeros. 3-0 lbec (11-8) latched bip-2 error counter: this is the upper nibble of a 12-bit shadow register which is updated from the bip-2 error counter once a second. the one-second interval is derived from the external one-second input, t1si. x+30 7-0 lfec (7-0) latched rei (febe) counter: this is the lower byte of a 12-bit shadow register which is updated from the rei (febe) counter once a second. the one-second interval is derived from the external one-second input, t1si. x+31 7-4 r reserved: these bits must be set to zeros. 3-0 lfec (11-8) latched rei (febe) counter: this is the upper nibble of a 12-bit shadow register which is updated from the rei (febe) counter once a second. the one-second interval is derived from the external one-second input, t1si. x+32 7-0 rxob(7-0) received o-bits: bits 3, 2, 1 and 0 are the first four o-bits (byte following j2, bits 3, 4, 5 and 6) incoming on dd(0-7). the second four o-bits (byte following z6/n2, bits 3, 4, 5 and 6) are placed in bits 7, 6, 5 and 4. x+33 7-0 rxj2(7-0) received j2 byte: bit 7 is bit 1 of the j2 byte incoming on dd(0-7). bit 0 is bit 8 of the j2 byte. x+34 7-0 rxz6(7-0) received z6/n2 byte: bit 7 is bit 1 of the z6/n2 byte incoming on dd(0-7). bit 0 is bit 8 of the z6/n2 byte. x+35 7-0 rxz7(7-0) received z7/k4 byte: bit 7 is bit 1 of the z7/k4 byte incoming on dd(0-7). bit 0 is bit 8 of the z7/k4 byte. address* bit symbol description
- 143 of 154 - txc-04201b-mb ed. 4, september 2001 ds1mx7 txc-04201b data sheet proprietary transwitch corporation information for use solely by its customers x+36 7-0 txob(7-0) transmit o-bits: bits 3, 2, 1 and 0 are the first four o-bits (byte following j2, bits 3, 4, 5 and 6). the second four o-bits (byte following z6/n2, bits 3, 4, 5 and 6) are bits 7, 6, 5 and 4. when obapen is set to zero, the micro- processor ? written data, in this location is output on ad(0-7). if obapen is set to one, the o-bit information is taken from the auxiliary port and is out- put on ad(0-7). it is also written here for access by the microprocessor. control bit tbtval (register x+05h bit 7) must be set to a "1" to be able to read this register after it is written. x+37 7-0 txj2(7-0) transmit j2 byte: bit 7 is bit 1 of the j2 byte and bit 0 is the bit 8 of the j2 byte. when j2apen is set to zero, the microprocessor-written data in this location, is output on ad(0-7). if j2apen is set to one, the j2 informa- tion is taken from the auxiliary port and output on ad(0-7). it is also written here for access by the microprocessor. control bit tbtval (register x+05h bit 7) must be set to a "1" to be able to read this register after it is written. x+38 7-0 txz6(7-0) transmit z6/n2 byte: bit 7 is bit 1 of the z6/n2 byte and bit 0 is bit 8 of the z6/n2 byte. when z6apen is set to zero, the microprocessor-written data, in this location, is output on ad(0-7). if z6apen is set to one, the z6/ n2 information is taken from the auxiliary port and output on ad(0-7). it is also written here for access by the microprocessor. control bit tbtval (register x+05h bit 7) must be set to a "1" to be able to read this register after it is written. x+39 7-0 txz7(7-0) transmit z7/k4 byte: bit 7 is bit 1 of the z7/k4 byte and bit 0 is bit 8 of the z7/k4 byte. when z7apen is set to zero, the microprocessor ? written data, in this location, is output on ad(0-7). if z7apen is set to one, the z7/ k4 information is taken from the auxiliary port and output on ad(0-7). it is also written here for access by the microprocessor. in either case, only bits 7-4 and 0 will appear in the output. bits 1, 2 and 3 are controlled by the transmit rdi circuity. for proper idle operation this register should be set to 00h. control bit tbtval (register x+05h bit 7) must be set to a "1" to be able to read this register after it is written. x+3a 7-4 r reserved: these bits have indeterminate status on read. 3 rgfebe-v ring port rei (febe) input: this location contains the information input at the ring port. control bit ringen (bit 4) in register x+0bh must be set to a one. 2 rgrdi-vpd ring port path defect input: this location contains the information input at the ring port. control bit ringen (bit 4) in register x+0bh must be set to a one. 1 rgrdi-vsd ring port server defect input: this location contains the information input at the ring port. control bit ringen (bit 4) in register x+0bh must be set to a one. 0 rgrdi-vcd ring port connectivity defect input: this location contains the informa- tion input at the ring port. control bit ringen (bit 4) in register x+0bh must be set to a one. x+3b - x+3f 7-0 reserved reserved: these registers should not be accessed. address* bit symbol description
- 144 of 154 - txc-04201b-mb ed. 4, september 2001 proprietary transwitch corporation information for use solely by its customers ds1mx7 txc-04201b data sheet application diagrams figure 48. ds1mx7 txc-04201b applications the application diagram in figure 48 shows four different uses for the ds1mx7. for sonet byte-synchronous application the ds1mx7 connected to the qt1f- plus provides for mapping seven ds1s byte-synchronously. liu control can be provided by either qt1f- plus or ds1mx7. for asynchronous mappings the ds1mx7 can connect directly to most commercial liu devices and control them. direct ds0 access is available for byte-syn- chronous mappings (external slip buffers are required for common clocks across more than 24 ds0s). with the qt1f- plus , ds0 access is also available from ds1s mapped asynchronously. note that a single ds1mx7 can support all applications simultaneously. the diagram in figure 49 illustrates some uses of the ds1mx7 device to provide framing and ds0 access for a variety of ds1 sources. direct control of most commercial line interface unit devices (lius) is provided. qt1f- plus txc-03103 ds1mx7 txc-04201b sot-3 txc-03003b syn155c txc-02302b sonet sts-3 ds1mx7 txc-04201b ds1mx7 txc-04201b ds1mx7 txc-04201b qt1f- plus txc-03103 liu liu liu liu liu liu liu liu liu 24 ds0+sig, clock & frame 24 ds0+sig, clock & frame 24 ds0+sig, clock & frame ds1(1) ds1(2) ds1(3) ds1(4) ds1(5) ds1(6) ds1(7) ds1(1) ds1(7) (async) (byte sync) (async) qt1f- plus txc-03103 (byte sync) or phast-3n txc-06103 sonet sts-3
- 145 of 154 - txc-04201b-mb ed. 4, september 2001 ds1mx7 txc-04201b data sheet proprietary transwitch corporation information for use solely by its customers figure 49. some ds1mx7 txc-04201b byte-synchronous applications ds1mx7 txc-04201b qt1f- plus txc-03103 sonet sts-3 syn155c txc-02302b sot-3 txc-03003b 1 1 8 21 80 ds1mx7 txc-04201b 12 84 1 liu dsx1 liu liu liu liu liu dsx1 o / e o / e e / o sot-1e (w to e) e / o ds1mx7 ds1mx7 liu liu * * * * * dsx-1 liu 1 dsx-1 liu 4 qt1f- tpos1 lt c l k 1 rpos1 lrclk1 lcs1 1 1 4 5 8 25 ring 28 plus oc1 oc1 ring port tneg1 dsx-1 dsx-1 tpos4 lt c l k 4 rpos4 lrclk4 lcs4 tneg4 tsigl5-tsigl1 tsync5-tsync1 ltclk5-tclk1 rsync5-rsync1 rsigl5-rsigl1 rpos5-rdata1 lrclk5-rclk1 tpos5-tdata1 rsigl1 rsync1 rclk1 tsync1 tsigl1 tdata1 tclk1 rdata1 rsigl4 rsync4 rclk4 tsync4 tsigl4 tdata4 tclk4 rdata4 rsigl4 rsync4 rclk4 tsync4 tsigl4 tdata4 tclk4 rdata4 rsigl1 rsync1 rclk1 tsync1 tsigl1 tdata1 tclk1 rdata1 2.048 mhz 8.0 khz to / fr o m d s 0 s w i t c h qt1f- plus qt1f- plus qt1f- plus qt1f- plus mvip mode mvip mode transmission mode: set ds1 transparent for asynch & esf tsigl4-tsigl4 tsync4-tsync4 ltclk4-tclk4 rsync4-rsync4 rsigl4-rsigl4 rpos4-rdata4 lrclk4-rclk4 tpos4-tdata4 tsigl1-tsigl1 tsync1-tsync1 ltclk1-tclk1 rsync1-rsync1 rsigl1-rsigl1 rpos1-rdata1 lrclk1-rclk1 tpos1-tdata1 tsigl7-tsigl3 tsync7-tsync3 ltclk7-tclk3 rsync7-rsync3 rsigl7-rsigl3 rpos7-rdata3 lrclk7-rclk3 tpos7-tdata3 dfail dclk dspe dc1j1v1 dd(0-7) dpar aclk ac1j1v1 aspe daten ad(0-7) apar aadd ds1mx7 ltc l k 1/ - lrclk1 tpos1/ - rpos1 rpos1/ - tpos1 lrclk1/ - ltclk1 lt c l k 4 / - lrclk4 tpos4/ - rpos4 rpos4/ - tpos4 lrclk4/ - ltclk41 lt c l k 1 / - lrclk1 tpos1/ - rpos1 rpos1/ -tpos1 lrclk1/ - ltclk1 for byte synch lt c l k 3 / - lrclk3 tpos3/ - rpos3 rpos3/ - tpos3 lrclk3/ - ltclk3 to/from liu for dsx-1 extra port from bits rpos4/ -lrclk4 ltclk4/lrclk4 rpos4/tpos4 microprocessor interface bits reference lo t1si srclk lo lo lo lo t1si t1si t1si t1si rclk4 transmission mode: set ds1 transparent for asynch & esf for byte synch byte-synchronous or asynchronous mapped ds1 to a mvip time switch byte-synchronous or asynchronous mapped ds1 to dsx-1 ring protected byte-synchronous or asynchronous mapped ds1 to dsx-1 terminal multiplexer phast-3n txc-06103 or sonet sts-3 phast-1 or or (t1fx8) (txc-03108) qt1f- plus txc-03103 or (t1fx8) (txc-03108) (11) sot-1e (e to w) phast-1 or t1fx8 or qt1f- plus t1fx8 or t1fx8 or t1fx8 or
- 146 of 154 - txc-04201b-mb ed. 4, september 2001 proprietary transwitch corporation information for use solely by its customers ds1mx7 txc-04201b data sheet package information the ds1mx7 device is packaged in a 208-pin plastic quad flat package (pqfp) suitable for surface mounting, as shown in figure 50. figure 50. ds1mx7 txc-04201b 208-pin plastic quad flat package 156 105 104 53 1 208 25.50 ref (sq) 28.00 0.10 (sq) 30.60 0.25 (sq ) 4.20 max 0.08 max (note 2) see detail ? a ? 0.16 0.60 0.20 0 o -7 o detail ? a ? 157 52 pin #1 index transwitch 0.50 typ 0.28 max (typ) see details ? b ? and ? c ? detail ? b ? detail ? c ? notes: 1. all linear dimensions are in millimeters and are nominal unless otherwise indi- cated. 2. coplanarity of all leads shall be within 0.1 millimeters (difference between the highest and lowest lead with seat- ing plane as reference). 0.17 min (typ) 3.67 max 0.25 min txc-04201bipq 3.17 min
- 147 of 154 - txc-04201b-mb ed. 4, september 2001 ds1mx7 txc-04201b data sheet proprietary transwitch corporation information for use solely by its customers ordering information part number: txc-04201bipq 208-pin plastic quad flat package related products txc-02020, art vlsi device (advanced sts-1/ds3 receiver/transmitter). art performs the transmit and receive line interface functions required for transmission of sts-1 (51.840 mbit/s) and ds3 (44.736 mbit/s) signals across a coaxial interface. txc-02021, arte vlsi device (advanced sts-1/ds3 receiver/transmitter). arte has the same functionality as art, plus extended features. txc-02302b, syn155c vlsi device (155-mbit/s synchronizer, clock and data output). this device provides a complete sts-3/stm-1 frame synchronization function in a single cmos unit. txc-03001b, sot-1 vlsi device (sonet sts-1 overhead terminator). performs section, line, and path overhead processing for sts-1 sonet signals. interfaces are provided for both section and line orderwire and datacom channels. further, control bits in the memory map enable the sot-1 to perform loopback and serial or parallel i/o. txc-03003b, sot-3 vlsi device (stm-1/sts-3/sts-3c overhead terminator). this is a program- mable device that performs section, line and path overhead processing for stm-1/sts-3/sts-3c signals. the sot-3 device performs pointer generation (with internal pointer justification) with respect to external clock timing in both the transmit and receive directions. txc-03011, sot-1e vlsi device (sonet sts-1 overhead terminator). this device provides extended features relative to the 84-lead txc-03001b sot-1 device, and it has a 144-lead pack- age. txc-03103, qt1f- plus vlsi device (quad t1 framer- plus ). a 4-channel framer for voice and data applications. this device handles all logical interfacing functionality to a t1 line. it operates from a power supply of 3.3 volts or 5 volts. txc-03108, t1fx8 vlsi device (8-channel t1 framer). an 8-channel framer for voice and data communications applications. this device handles all logical interfacing functionality to a t1 line and operates from a power supply of 3.3 volts. txc-04251, qt1m vlsi device (quad ds1 to vt1.5 or tu-11 async mapper-desync). intercon- nects four ds1 signals with any four asynchronous mode vt1.5 or tu-11 tributaries carried in sonet sts-1 or sdh au-3 rate payload interface. txc-04228, t1mx28 vlsi device (ds1 mapper 28-channel device). the t1mx28 maps twenty eight ds1 signals into any seven selected asynchronous or byte-synchronous mode vt1.5 or tu-11 tributaries in a sonet/sdh synchronous payload envelope. t1mx28 is four ds1mx7 devices com- bined into one package. txc-06101, phast-1 vlsi device (sonet sts-1 overhead terminator). this device provides features similar to those of the txc-03011 sot-1e device, but it operates from a power supply of 3.3 volts rather than 5 volts. txc-06103, phast-3n vlsi device (sonet stm-1, sts-3 or sts-3c overhead terminator). this phast-3n vlsi device provides a telecom bus interface for downstream devices. it operates from a power supply of 3.3 volts.
- 148 of 154 - txc-04201b-mb ed. 4, september 2001 proprietary transwitch corporation information for use solely by its customers ds1mx7 txc-04201b data sheet standards documentation sources telecommunication technical standards and reference documentation may be obtained from the following organizations: ansi (u.s.a.): american national standards institute tel: (212) 642-4900 11 west 42nd street fax: (212) 302-1286 new york, new york 10036 web: www.ansi.org the atm forum (u.s.a., europe, asia): 2570 west el camino real tel: (650) 949-6700 suite 304 fax: (650) 949-6705 mountain view, ca 94040 web: www.atmforum.com atm forum europe office av. de tervueren 402 tel: 2 761 66 77 1150 brussels fax: 2 761 66 79 belgium atm forum asia-pacific office hamamatsu-cho suzuki building 3f tel: 3 3438 3694 1-2-11, hamamatsu-cho, minato-ku fax: 3 3438 3698 tokyo 105-0013, japan bellcore (see telcordia) ccitt ( see itu-t) eia (u.s.a.): electronic industries association tel: (800) 854-7179 (within u.s.a.) global engineering documents tel: (314) 726-0444 (outside u.s.a.) 7730 carondelet avenue, suite 407 fax: (314) 726-6418 clayton, mo 63105-3329 web: www.global.ihs.com etsi (europe): european telecommunications standards institute tel: 4 92 94 42 22 650 route des lucioles fax: 4 92 94 43 33 06921 sophia antipolis cedex web: www.etsi.org france
- 149 of 154 - txc-04201b-mb ed. 4, september 2001 ds1mx7 txc-04201b data sheet proprietary transwitch corporation information for use solely by its customers go-mvip (u.s.a.): the global organization for multi-vendor integration protocol (go-mvip) tel: (800) 669-6857 (within u.s.a.) tel: (903) 769-3717 (outside u.s.a.) 3220 n street nw, suite 360 fax: (508) 650-1375 washington, dc 20007 web: www.mvip.org itu-t (international): publication services of international telecommunication union tel: 22 730 5111 telecommunication standardization sector fax: 22 733 7256 place des nations, ch 1211 web: www.itu.int geneve 20, switzerland mil-std (u.s.a.): dodssp standardization documents ordering desk tel: (215) 697-2179 building 4 / section d fax: (215) 697-1462 700 robbins avenue web: www.dodssp.daps.mil philadelphia, pa 19111-5094 pci sig (u.s.a.): pci special interest group tel: (800) 433-5177 (within u.s.a.) 2575 ne kathryn street #17 tel: (503) 693-6232 (outside u.s.a.) hillsboro, or 97124 fax: (503) 693-8344 web: www.pcisig.com telcordia (u.s.a.): telcordia technologies, inc. tel: (800) 521-core (within u.s.a.) attention - customer service tel: (908) 699-5800 (outside u.s.a.) 8 corporate place fax: (908) 336-2559 piscataway, nj 08854 web: www.telcordia.com ttc (japan): ttc standard publishing group of the telecommunications technology committee tel: 3 3432 1551 fax: 3 3432 1553 2nd floor, hamamatsu-cho suzuki building, web: www.ttc.or.jp 1 2-11, hamamatsu-cho, minato-ku, tokyo
- 150 of 154 - txc-04201b-mb ed. 4, september 2001 proprietary transwitch corporation information for use solely by its customers ds1mx7 txc-04201b data sheet list of data sheet changes this change list identifies those areas within this updated ds1mx7 data sheet that have significant differ- ences relative to the previous and now superseded ds1mx7 data sheet: updated ds1mx7 data sheet: ed. 4, september 2001 previous ds1mx7 data sheet: ed. 3, november 2000. the page numbers indicated below of this updated data sheet include changes relative to the previous data sheet. page number of updated data sheet summary of the change all changed edition number and date. 11 changed the fifth paragraph which begins ? the vt termination block... ? 21 for the symbol aadd , removed tristate designation from the i/o/p column and changed the last line of the description. 33 changed the min times for t h(1) , t h(2) , and t h(3) in figure 8 to 6.0 ns. 34 changed the min times for t h(1) , t h(2) , and t h(3) in figure 9 to 6.0 ns. 44 added t h(2) to the timing diagram and table in figure 19 for addr (0-8). 57 changed the 9 th sentence of the third paragraph, to read ? for true byte- synchronous operation.... ? . 67 changed the pointer leak rate algorithm description notes 5, 6, 7, and 8 in figure 29. 82 in description for figure 40, replaced the last sentence with four new ones. 97 for boundary scan cell # 68, changed i/o from output1 to output. 143 in description for registers x+36 through x+39 added new last sentence. 147 deleted last entry under related products (txc-06112). 150 replaced ? list of data sheet changes ? section.
- 151 of 154 - txc-04201b-mb ed. 4, september 2001 ds1mx7 txc-04201b data sheet proprietary transwitch corporation information for use solely by its customers - notes - transwitch reserves the right to make changes to the product(s) or cir- cuit(s) described herein without notice. no liability is assumed as a result of their use or application. transwitch assumes no liability for transwitch applications assistance, customer product design, software performance, or infringement of patents or services described herein. nor does transwitch warrant or represent that any license, either express or implied, is granted under any patent right, copyright, mask work right, or other intellectual property right of transwitch covering or relating to any combination, machine, or process in which such semiconductor products or services might be or are used.
transwitch corporation ? 3 enterprise drive shelton, ct 06484 usa www.transwitch.com tel: 203-929-8810 fax: 203-926-9453
- 153 of 154 - txc-04201b-mb ed. 4, september 2001 ds1mx7 txc-04201b data sheet proprietary transwitch corporation information for use solely by its customers documentation update registration form if you would like to receive updated documentation for selected devices as it becomes available, please provide the information requested below (print clearly or type) then tear out this page, fold and mail it to the marketing communications department at transwitch. marketing communications will ensure that the relevant product information sheets, data sheets, application notes, technical bulletins and other publications are sent to you. you may also choose to provide the same information by fax (203.926.9453) , or by e-mail (info@txc.com) , or by telephone (203.929.8810) . most of these documents will also be made immediately available for direct download as adobe pdf files from the transwitch world wide web site ( www.transwitch.com ). name: ________________________________________________________________________________ company: ___________________________________________ title: ______________________________ dept./mailstop: __________________________________________________________________________ street: ________________________________________________________________________________ city/state/zip: __________________________________________________________________________ if located outside u.s.a., please add - country: _______________ postal code: ___________________ telephone: ________________________ ext.: _____________ fax: __________________________ e-mail: ________________________________________________ please provide the following details for the managers in charge of the following departments at your company location. department title name company/division __________________ __________________ engineering __________________ __________________ marketing __________________ __________________ please describe briefly your intended application(s) and indicate whether you would like to have a transwitch applications engineer contact you to provide further assistance: _____________________________________________________________________________________________ ____________________________________________________________________________________________ ____________________________________________________________________________________________ ____________________________________________________________________________________________ if you are also interested in receiving updated documentation for other transwitch device types, please list them below rather than submitting separate registration forms: __________ __________ __________ __________ __________ __________ __________ __________ __________ __________ __________ __________ __________ __________ please fold, tape and mail this page (see other side) or fax it to marketing communications at 203.926.9453.
transwitch corporation attention: marketing communications dept. 3 enterprise drive shelton, ct 06484-4694 u.s.a. first class postage required please complete the registration form on this back cover sheet, and mail or fax it, if you wish to receive updated documentation on selected transwitch products as it becomes available. (fold back on this line first.) (fold back on this line second, then tape closed, stamp and mail.) transwitch corporation 3 enterprise drive shelton, ct 06484 usa www.transwitch.com tel: 203-929-8810 fax: 203-926-9453 3 enterprise drive shelton, ct 06484-4694 u.s.a.

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